CIRCUIT ANALYSIS METHODOLOGY FOR
ORGANIC TRANSISTORS
—
METHODIK ZUR SCHALTUNGSANALYSE FÜR
ORGANISCHETRANSISTOREN
Der Technischen Fakultät der
Universität Erlangen-Nürnberg
zur Erlangung des Grades
DOKTOR – INGENIEUR
vorgelegt von
Jürgen KrummErlangen – 2008
Als Dissertation genehmigt von
der Technischen Fakultät der
Universität Erlangen-Nürnberg
Tag der Einreichung: 26.11.2007
Tag der Promotion: 03.03.2008
Dekan: Prof. Dr.-Ing. habil. J. Huber
Berichterstatter: Prof. Dr.-Ing. W. H. Glauert
Prof. Dr.-Ing. habil. R. Weigel
I
Danksagung
Diese Arbeit entstand als Ergebnis meiner wissenschaftlichen Tätigkeit am Lehrstuhl für
Rechnergestützten Schaltungsentwurf der Friedrich-Alexander-Universität Erlangen-Nürnberg.
Ich bedanke mich bei Herrn Prof. Dr.-Ing. Wolfram H. Glauertfür die hervorragende Be-
treuung und Begutachtung dieser Arbeit. Für die freundliche Übernahme des Zweitgutachtens
danke ich Herrn Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel. Bei den folgenden Personen
bedanke ich mich für die vielen fachlichen Diskussionen bzw. für das Korrekturlesen von
Kapiteln meiner Arbeit: Ahmed Amar, Dr. Robert Blache, Dr.-Ing. Markus Böhm, Dr. Hen-
ning Rost, Katharina Schätzler, Wolfgang Schirmer und Dr. Dietmar Zipperer. Ferner gilt
mein Dank den Lehrstuhlkollegen Elke Eckert, Wolfgang Magerl und Klaus Schneider, mit
denen ich an verschiedenen Projekten aus der Polymerelektronik arbeiten durfte. Besonders
bedanken möchte ich mich auch bei meinen Zimmerkollegen Thomas Bürner, Werner Haas
und Reinhard Hofmann für das nette Arbeitsumfeld. Für die organisatorische Hilfe im Vor-
feld und während der Promotionsprüfung bedanke ich mich beiFrau Roswitha Rauch, der
Sekretärin des Lehrstuhls.
Schließlich danke ich meiner Familie für ihre Unterstützung.
Erlangen, Mai 2008
Jürgen Krumm
II
Contents III
Contents
1 Introduction 1
1.1 Circuit Simulation in the Optimization of OFETs . . . . . . .. . . . . . . . 2
1.2 Aim of this Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Scientific Contribution of this Work . . . . . . . . . . . . . . . . .. . . . . 4
1.4 Outline of this Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Concepts of Low-Cost Organic Electronics 7
2.1 State of the Art in Organic Circuits . . . . . . . . . . . . . . . . . .. . . . . 7
2.2 Organic Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8
2.2.1 Oligomers and Polymers . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 Unipolar and Ambipolar Semiconductors . . . . . . . . . . . .. . . 9
2.2.3 Charge Transport Models . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Organic Field-Effect Transistors . . . . . . . . . . . . . . . . . .. . . . . . 11
2.3.1 Device Characteristics of an OFET . . . . . . . . . . . . . . . . .. 11
2.3.2 Differences between MOSFET and OFET . . . . . . . . . . . . . . .13
2.4 Printing and Roll-to-Roll Fabrication . . . . . . . . . . . . . .. . . . . . . . 15
2.5 Chapter Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3 OFET Modeling for Circuit Simulation 19
3.1 Model Requirements for Circuit Simulation . . . . . . . . . . .. . . . . . . 19
3.2 Existing Models for OFETs . . . . . . . . . . . . . . . . . . . . . . . . . .. 21
3.2.1 Shichman-Hodges Model (Level-1 Model) . . . . . . . . . . . .. . 22
3.2.2 Model for Polycrystalline TFTs . . . . . . . . . . . . . . . . . . .. 27
3.2.3 Model for Amorphous TFTs . . . . . . . . . . . . . . . . . . . . . . 32
3.2.4 Analytic VRH Models . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2.5 General Table-based Models . . . . . . . . . . . . . . . . . . . . . .43
3.2.6 Dresden Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2.7 Modeling of Complementary OFETs . . . . . . . . . . . . . . . . . 46
3.2.8 Modeling of Ambipolar OFETs . . . . . . . . . . . . . . . . . . . . 48
IV Contents
3.3 Popular Procedures for Parameter Extraction . . . . . . . . .. . . . . . . . . 50
3.3.1 Procedures for the Level-1 Model . . . . . . . . . . . . . . . . . .. 50
3.3.2 Extraction Procedures for TFT Models . . . . . . . . . . . . . .. . 59
3.3.3 Parameter Fitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4 Automation of Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.4.1 Existing Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.4.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4 VSat Method 69
4.1 Extraction based onVSat Method . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2 Modeling based onVSat Method . . . . . . . . . . . . . . . . . . . . . . . . 73
4.2.1 VSat-Type Table-Based Model . . . . . . . . . . . . . . . . . . . . . 73
4.2.2 Linvar Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3 Experimental Results on Transistor Fitting . . . . . . . . . .. . . . . . . . . 76
4.3.1 Analysis of a Level-1 Transistor . . . . . . . . . . . . . . . . . .. . 76
4.3.2 Analysis of Model for Polycrystalline TFTs . . . . . . . . .. . . . . 77
4.3.3 Effect of Contact Resistance on Level-1 Model . . . . . . .. . . . . 81
4.3.4 Compensation of Contact Resistance . . . . . . . . . . . . . . .. . . 82
4.3.5 Analysis of a PDHTT Transistor . . . . . . . . . . . . . . . . . . . .87
4.3.6 Modeling of a P3HT Transistor . . . . . . . . . . . . . . . . . . . . 87
4.3.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5 Analysis of OFET-Based Logic Circuits 93
5.1 Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1.1 Basic Circuit Concepts . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1.2 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.2 Circuit Characterization . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 97
5.3 Characterization of Robustness . . . . . . . . . . . . . . . . . . . .. . . . . 99
5.3.1 Method of Equilibrium Zones . . . . . . . . . . . . . . . . . . . . . 99
5.3.2 Concept of Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . 102
5.3.3 Unity Gain Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3.4 Method of Maximum Squares . . . . . . . . . . . . . . . . . . . . . 106
5.3.5 VTC Gain Considerations . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.6 Discussion of Characterization Methods . . . . . . . . . . .. . . . . 110
5.4 Timing Characterization . . . . . . . . . . . . . . . . . . . . . . . . . .. . 112
5.5 Automation of Circuit Characterization . . . . . . . . . . . . .. . . . . . . 115
Contents V
5.5.1 Tools for Characterization of Logic Circuits . . . . . . .. . . . . . . 115
5.5.2 General Characterization Tools . . . . . . . . . . . . . . . . . .. . . 116
5.5.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6 Analysis Concept 121
6.1 Typical Analysis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
6.2 Novel Analysis Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
6.2.1 Data Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2.2 Modeling System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.2.3 Analysis Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.2.4 Simulator Encapsulation . . . . . . . . . . . . . . . . . . . . . . . .135
6.3 Analysis Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.1 Analysis of an Inverter in Current-Source Configuration . . . . . . . 136
6.3.2 Analysis of NOR-Gates in Current-Source Configuration . . . . . . . 143
6.3.3 Analysis of Parameter-dependent Gate Behavior . . . . .. . . . . . 146
6.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7 Summary and Further Work 151
7.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7.2 Further Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
A List of Symbols 155
B List of Acronyms 161
C Glossary 163
D Symbols and Truth Tables for Logic Circuits 167
E Simulation Software 169
Bibliography 170
VI
VII
Abstract
In this work, a novel computer-aided methodology for the analysis of the performance of
organic transistors (OFETs) in logic circuits is described. The basic idea of the concept is to
provide an integrated environment which includes data management, modeling of transistors,
and the automatic analysis of organic circuits. Existing OFET models as well as procedures
and software tools for extracting their model parameters are analyzed. A novel formalism
which compares the quality of models is defined using a model quality chart. Furthermore, a
novel method of extracting basic model parameters in dependence on the gate-source voltage
is detailed. It aids in visualizing which type of model best maps a given transistor. Two
transistor models are presented: a table-based model and ananalytical model. Procedures for
characterizing static and dynamic behavior of basic logic circuits are discussed as well as tools
for deriving appropriate performance figures. Novel methods of extracting the robustness
of logic gates are presented. Several examples demonstratethe application of the analysis
methodology to organic logic circuits and OFET modeling issues, respectively.
Kurzfassung
In dieser Arbeit wird eine neue, Computer-gestützte Methodik zur Performanceanalyse von
organischen Transistoren (OFETs) in Logikschaltungen beschrieben. Das Konzept basiert
auf der Grundidee, eine integrierte Umgebung für die Datenverwaltung, die Modellierung
von Transistoren und die automatische Analyse organischerSchaltungen bereitzustellen. Ex-
istierende OFET-Modelle sowie Prozeduren und Software-Werkzeuge zur Extraktion der zuge-
hörigen Modellparameter werden untersucht. Ein neuer Formalismus, um die Qualität einzel-
ner Modelle mit Hilfe einer Qualitätscheckliste zu vergleichen, wird definiert. Ein neues Ver-
fahren zur Extraktion grundlegender Modellparameter in Abhängigkeit von der Gate-Source-
Spannung wird beschrieben. Das Verfahren visualisiert, durch welchen Modelltyp ein ge-
gebener Transistor am besten abgebildet werden kann. Zwei Transistormodelle werden vorge-
stellt: ein Tabellenmodell und ein analytisches Modell. Verfahren und Software-Werkzeuge,
um das statische und dynamische Verhalten grundlegender Logikschaltungen zu charakter-
isieren und zugehörige Kennzahlen zu ermitteln, werden diskutiert. Neue Methoden zur Bes-
timmung der Gatterrobustheit werden vorgestellt. MehrereBeispiele zeigen die Anwendung
der Analysemethodik bei organischen Logikschaltungen bzw. bei Fragestellungen der OFET-
Modellierung.
VIII
1
Chapter 1
Introduction
The field of low-cost organic electronics is a relatively newtopic of research in the domain
of semiconductor technology. Activities started in the 1980s by demonstrating organic field-
effect transistors (OFETs) which make use of special organic compounds for the semiconduct-
ing channel instead of crystalline silicon. These OFETs cannot compete with silicon-based
transistors regarding switching speed or packing density but provide prospects of consider-
ably reducing fabrication costs, large-area manufacturing (i.e. direct application of electronic
structures onto large substrates), or implementing mechanically flexible integrated circuits.
These advantages generate applications of OFETs where fabrication costs or flexibility are
more important than e.g. switching speed of the transistors. One example is the implemen-
tation of extremely low-cost radio-frequency identification (RFID) tags. Fabrication costs
below one Cent would e.g. boost application of RFID devices as price tags in supermarkets.
Owing to their complex fabrication, silicon-based RFID tags cannot reach this price target.
Currently, low-cost organic electronics is in the early stages of development and optimiza-
tion of devices and processes. Various materials and fabrication processes are continuously
tested and optimized. Circuit simulation is an important part in this process as it provides
insight into the performance potential of existing or hypothetical OFET generations in OFET-
based circuits. In the course of circuit simulation, devices are modeled and the electrical
performance of typical application circuits is analyzed. Employing circuit simulation in the
process of optimizing devices consists of numerous iterations of modeling devices, simulating
application circuits, and extracting performance figures from simulation results. Therefore,
efficient methods of modeling OFET devices and analyzing OFET-based circuits by use of
circuit simulation are needed in order to automate the analysis process as much as possible.
This thesis describes a methodology for efficient modeling of OFETs and analysis of
OFET-based logic circuits. The basic idea is to provide a uniform analysis environment which
seamlessly integrates transistor modeling, circuit analysis of OFET-based circuits, and neces-
sary data management.
2 Chapter 1. Introduction
1.1 Circuit Simulation in the Optimization of OFETs
Fig. 1.1 shows where circuit simulation can be used in the evaluation of an OFET process.
The flow consists of manufacturing OFETs, characterizing their electrical performance or
long-term stability, and subsequently improving the process, which leads to new iterations of
the procedure.
Circuit Simulation
leads to
includes
includes
Models
Benchmark
Testbenches
improvementsProcess
fabricationDevice
characterizationDevice
analysisPerformance
circuits
extractionParameter
OFET
Testbench
Circuit
Reporting
modeling
generation
characterization
Fig. 1.1: Generic analysis flow showing the evaluation of theelectrical performance of novelOFET technologies by use of circuit simulation.
In the depicted flow, device characterization and performance analysis include circuit sim-
ulation (shaded box in the figure) where device parameters like threshold voltage or charge-
carrier mobility are extracted. From these parameters, simulation models are generated for
the OFET devices. Depending on the fabrication technology,different transistor models are
needed. Devices fabricated in a certain layer setup (bottomgate / bottom contact structure
[2, 3], see Section 2.3.1) e.g. display substantial contactresistance between the electrodes
and the channel. Models and their parameters are used in the analysis ofbenchmark circuits.
The term benchmark circuit refers to the fact that these circuits are used for the evaluating
and comparing different device generations. Benchmarkingshould be carried out with typical
application circuits like OFET-based logic circuits. Analysis of benchmark circuits requires
suitabletestbenches. A testbench is a circuit setup containing the benchmark circuits and ad-
1.1. Circuit Simulation in the Optimization of OFETs 3
ditional circuitry used for extracting performance figures. Performance figures related to logic
circuits are e.g. robustness of the desired logic function against interfering noise at the inputs
and outputs of the gates, circuit speed, power consumption,etc. These performance figures
can be established using a technique calledcircuit characterizationor cell characterization.
Circuit characterization provides information on the electrical properties of the circuits un-
der consideration like input capacitances, timing data, orpower consumption at reasonable
operating conditions.
The performance figures of the analyzed circuits can be compared with data derived by
analyzing earlier device generations. This approach is helpful when measuring the improve-
ments between different device generations but is also useful in selecting the most efficient
solution from a list of possible circuit concepts for a givenprocess.
Traditional software tools from the domain of electronic design automation (EDA) easily
cover the circuit simulation tasks depicted in Fig. 1.1. Several problems arise when working
with standard software:
2 Existing software for model extraction is currently not well adapted to OFET devices.
OFET-based transistor models are missing and would have to be included into the ex-
tractors.
2 Tools for circuit characterization are normally adapted tohigh-speed state-of-the-art
circuits. They do not include simple analyses like the determination of the maximum-
square noise margin (see Section 5.3.4). Including new analyses into existing tools is
often difficult as the source code of the programs is not disclosed or would have to be
reworked.
2 Collaboration between different tools is necessary. Data from the model extractor would
have to be transferred to the testbenches used by the characterization tool and charac-
terization results would have to be displayed and archived for documentation and later
reuse.
2 Data organization is up to the user. The optimization of OFETdevices and organic logic
gates leads to many iterations of measurement, model extraction, and circuit analysis.
The respective data have to be stored in an efficient way. Prior analysis results must
be accessible later on in order to explore the effects of optimization steps in the fab-
rication process. Moreover, analysis procedures might change because new figures of
merit are introduced. In such a case, prior analyses need to be repeated with the new
characterization flow.
2 The characterization flow depends on the different tools used in the analysis process.
These tools are coordinated by control scripts. As soon as vendors change their tools
4 Chapter 1. Introduction
the characterization flow has to be updated, including the control scripts. Moreover,
migration to other tools would also require recoding of scripts. Additionally, the users
need to understand the inner workings of the tools in order toinclude them in their
analysis flow.
Therefore, it is desirable to integrate the required tools into a coherent, generic, and flex-
ible framework. Coherent means that the framework seamlessly integrates the different tools
and also covers data management. Generic means that the tools are integrated using abstract
interfaces so that they can easily be replaced. Novel tools can then be integrated by including
appropriate interfaces. Flexible means that the users can add novel characterization scripts by
use of easily adaptable interfaces.
1.2 Aim of this Thesis
In this thesis, a computer-aided methodology for modeling of OFETs and analyzing their
performance in logic circuits is presented. Development ofthe methodology leads to research
in the following domains:
2 Modeling: Examination of OFET models suitable in circuit simulation and of proce-
dures for extracting their parameters.
2 Circuit characterization: Definition of characterizationcriteria for circuits. In this work,
low-complexity logic circuits are in focus.
2 Analysis concept: Development of an analysis flow for carrying out parameter extrac-
tion for OFET models and logic gate characterization as wellas data management.
1.3 Scientific Contribution of this Work
Progress in the simulation-based modeling and circuit analysis of organic transistors could be
made in this work. First, a checklist toassess the quality of a modeling approachfor OFET
devices in logic circuits has been defined in the model quality chart (MQC). The MQC allows
its users to compare different modeling approaches. Formalisms like the MQC did not exist
before in the domain of organic electronics.
Second, a novel methodology for extracting device parameters in a two-step approach has
been developed. In a first step, the transistor characteristics drain-current (ID) vs. drain-source
voltage (VDS) are inspected. For eachID curve, the transition pointVSat between linear and
saturation region is extracted using a one-dimensional search. VSat and the measurement data
are then used for calculating three basic transistor parameters: threshold voltageVT , process
1.4. Outline of this Work 5
conductanceKP , and channel-length modulationλ. The gate-voltage dependent shapes of
these parameters extracted for a series ofID curves are characteristic for different model types.
Therefore, they can be used for identifying themodel which maps best the measured curves.
This approach contrasts with other analysis procedures which concentrate on the problem
which set of parameters maps best the measured curves for a given model. In a second step,
the extractedVGS-dependent parameters can be mapped to simulation models, e.g. the ones
developed in this work: a table-based model and a fitting-based analytic model.
Third, progress has been made in the analysis of OFET-based logic gates. A novel ap-
proach has been introduced to define the robustness of logic gates by inspecting the gain of
the fix point in the voltage-transfer characteristic. An existing method to qualitatively define
the compatibility of valid logic level ranges has been extended to yield noise margins.
A computer-aided methodologyhas been developed to run data storage, OFET model-
ing, automatic testbench generation, and circuit characterization within a single environment.
The novelty of the concept is the integration of these tasks by use of appropriate data struc-
tures. Moreover, a graphical scripting system has been integrated into the concept so to allow
non-expert users to flexibly compose their own characterization schemes. Existing tools and
analysis methods have been adapted to the analysis of OFET-based logic circuits.
1.4 Outline of this Work
In Chapter 2, the basics of low-cost organic electronics aresketched with focus on OFETs
and OFET-based logic circuits. Chapter 3 deals with the modeling of OFETs. Here, general
requirements on transistor models are described and existing models for organic transistors are
discussed. Moreover, existing procedures and tools for modeling of transistors are reviewed.
A novel methodology for translating measured transistor characteristics into model parameters
and two new transistor models based on this methodology are detailed in Chapter 4. Here,
selected analysis examples are presented where the methodology is applied. Next, OFET-
based logic circuits and the way how to characterize their static and dynamic behavior are
discussed in Chapter 5. Existing tools for circuit characterization are presented. A novel
analysis concept is then detailed in the first part of Chapter6. This concept implements
a computer-aided methodology for modeling of OFETs and analysis of OFET-based logic
circuits. In the second part of the chapter, sample sessionsdemonstrate the application of the
analysis concept in a prototype implementation. Chapter 7 concludes the work by presenting
a summary of the work and an outlook to further developments.
6 Chapter 1. Introduction
7
Chapter 2
Concepts of Low-Cost Organic
Electronics
In recent years, electronic devices based on organic materials have appeared in real appli-
cations. Displays composed of organic light emitting diodes (OLEDs) provide images with
increased brilliance when compared to more traditional display technologies. Small OLED-
based displays have already been commercially introduced.In organic photovoltaics, solar
cells are developed where organic semiconductors are used as the active layer. Moreover,
organic materials are considered for use in non-volatile memories. Another important focus
are integrated circuits (ICs) based on OFETs, which are currently in the development stage.
In the following, the concepts of organic electronics will be briefly introduced. More detailed
descriptions can be found in the references provided in the respective paragraphs. The dis-
cussion will focus on items relevant for low-cost organic transistors (OFETs), which are the
basic building blocks of organic integrated circuits.
2.1 State of the Art in Organic Circuits
The major advantage of organic electronics is ease of fabrication instead of improved electrical
performance of a device. A large number of organic materialscan be deposited from solution,
enabling e.g. application of high-speed and high-throughput printing methods. With increased
fabrication speed and output, lower fabrication costs are possible.
Organic ICs e.g. target smart price tags (also called RFID tags or transponders) as applica-
tion. These transponders can be electronically interrogated using a reader and radio frequency
communication. The organic RFID transponders draw their energy from the RF field of the
reader and consist of an antenna, organic rectifiers and an OFET-based logic block for trans-
mitting their information to the reader.
8 Chapter 2. Concepts of Low-Cost Organic Electronics
Prototype RFID tags with organic logic chips have lately been presented [4, 5], partially
fabricated using clean-room techniques. Yet, fully-printed circuits currently lag behind these
complexities and performances. In the domain of low-cost mass printed circuits, state-of-
the-art results were obtained with gravure printed polyfluorene (F8T2) as semiconductor and
offset printed PEDOT-PSS as source-drain material [6]. Measurement results of a seven-stage
ring oscillator1 were presented with an oscillation frequency of 1.2 Hz at a supply voltage of
48 V. Details about the early stages of the underlying fabrication process were presented in
[7]. Another group [8] reported results for a printed seven-stage ring oscillator with polytri-
arylamide (PTAA) as semiconductor. The oscillation frequency was 67 Hz at a supply voltage
of 30 V.
2.2 Organic Semiconductors
In the following, a brief introduction into organic semiconductors and popular models to de-
scribe their charge-transport mechanisms is given.
2.2.1 Oligomers and Polymers
Organic semiconductors are the most important materials for the functional layer of organic
transistors used in organic electronics. They are molecules consisting of a repetition of carbon-
based compounds with low molecular weight (called repetition units or monomers). Depend-
ing on the number of repetition unitsn, organic semiconductors belong to one of two cate-
gories: oligomers or polymers. Anoligomeris a compound withn usually less than about 10
to 15. Most oligomers cannot be deposited from solution because they are not very soluble in
common solvents [9]. Instead, they are deposited e.g. by vacuum deposition. Semiconduct-
ing oligomers show superior electrical performance (e.g. switching speed) when compared to
semiconducting polymers. Popular oligomers with semiconducting properties are e.g. pen-
tacene or oligothiophenes. Apolymeron the other hand is a compound with a higher number
of repetition units. More precisely, a polymer can be definedas a compound where adding a
new repetition unit will not alter its chemical and electrical behavior [10]. In order to make
polymers soluble in a variety of solvents and provide film forming properties, side chains are
chemically attached to the polymer chain so to allow deposition e.g. by printing methods. A
popular organic semiconductor is the p-type semiconducting polymer poly(3-hexylthiophene)
or P3HT in short. The basic building block of P3HT is thiophene, a ring of four carbon atoms
and one sulfur atom. A hexyl (C6H13) side chain is added to the thiophene ring in order to
1An oscillator circuit where seven inverters are cascaded and the output of the last inverter is fed back to theinput of the first inverter.
2.2. Organic Semiconductors 9
allow P3HT to be soluble in organic solvents. Fig. 2.1 shows the chemical structure of P3HT.
In the figure,n denotes the number of repetition units.
)( SS
C6H13
C6H13
n
Fig. 2.1: Chemical structure of poly(3-hexylthiophene).
Semiconducting polymers have aconjugated polymer backbone, i.e. an alternating se-
quence of single and double carbon-carbon bonds. Conjugation leads to the presence of delo-
calized molecular orbitals in the material where electronsbelong to a group of atoms instead
of a single bond or atom [11]. These electrons are important for charge transport.
2.2.2 Unipolar and Ambipolar Semiconductors
The majority of organic semiconductors displays unipolar p-type transport, i.e. hole trans-
port. There also exist unipolar n-type transport materialswhich show electrical performance
and lower stability under normal environmental conditions, however. Recently, ambipolar
semiconductors (e.g. [12, 13]) have been reported where both n-type and p-type charge trans-
port is possible. These materials are nevertheless in the early stages of research. They are
either intrinsically ambipolar or consist of mixtures of p-type and n-type conducting semicon-
ductors.
2.2.3 Charge Transport Models
Numerous models have been developed to deal with the mechanisms of charge transport
within organic semiconductors. The most popular of these are listed in the following.
Band Transport
By combining atoms into molecules, molecular orbitals are created. The highest molecular
orbital filled with electrons is denoted as HOMO (highest occupied molecular orbital) and the
lowest molecular orbital devoid of electrons as LUMO (lowest unoccupied molecular orbital).
HOMO and LUMO in organic semiconductors are used analogous to the opposing edges of
the valence and conduction bands in more traditional semiconductors. They are separated by
an energy gap.
10 Chapter 2. Concepts of Low-Cost Organic Electronics
Generally, the electronic properties of a semiconductor are strongly influenced by the
positions and distances of the opposing edges of the valenceand conduction band. Charge
transport of holes in the valence band and of electrons in theconduction band is limited by
scattering of the charge carriers at lattice vibrations or impurities. The mobility of charge
carriers decreases with elevated temperature because lattice vibrations are less pronounced at
lower temperatures.
Hopping Transport
Many organic semiconductors are regarded as disordered systems where band transport does
not seem reasonable between different molecules. Here, hopping transport provides a better
description of charge transport. In this model, free movement of charge carriers is not possible.
Instead, they hop between neighboring hopping sites. When acharge carrier hops to another
site, its presence there leads to a local deformation of the polymer. The pair of charge carrier
and deformation is calledpolaronand is modeled as a single quasi-particle. In order to move
between sites, the polaron has to overcome an energy barrier. The probability of crossing this
energy barrier and hopping between sites increases with elevated temperatures.
Multiple Trapping and Release
In the model of multiple trapping and release (MTR), charge carriers are assumed to travel by
band transport. This transport is impeded by the presence oftraps near the band edges. These
traps are energy levels within the bandgap which are caused by the presence of impurities or
structural defects [14]. When a charge carrier “falls” intosuch a trap, it is not available for
charge transport until it gets released again after a certain amount of time, e.g. by thermal
activation. The trapping time depends on the temperature and the energetic depth of the trap.
Grain Boundary Model
In polycrystalline organic semiconductors, the semiconductor film is composed of crystallites
which are separated by amorphous grain boundaries. While the charge carriers are assumed
to move freely in bands in the crystallites, they get trappedand released at traps in the grain
boundaries. These traps are due to the structural disorder at the interfaces of neighboring
grains. The traps in the grain boundaries get charged by capturing charge carriers. This
trapping creates a depletion region which in turn leads to the formation of an energy barrier.
Charge carriers have to overcome this energy barrier in order to travel across the depletion
region. The grain boundary model can be assumed as a special variation of MTR where traps
concentrate at the grain boundaries.
2.3. Organic Field-Effect Transistors 11
2.3 Organic Field-Effect Transistors
Organic semiconductors find application in organic field-effect transistors. OFETs have many
similarities with more traditional MOSFETs but also considerably differ from these. In the
following, the basic properties of OFETs and their differences to MOSFETs are briefly dis-
cussed.
2.3.1 Device Characteristics of an OFET
In Fig. 2.2, circuit symbol as well asoutput characteristicsID vs. VDS andtransfer charac-
teristicsID vs. VGS of an OFET are sketched. For the output characteristics,VDS is swept
in the range of interest at constantVGS values. The transfer characteristics are obtained by
applying a fixedVDS and sweepingVGS in the range of interest.
The schematic plots show the behavior of an n-type (electrontransport) OFET with pos-
itive voltages. P-type (hole transport) FETs operate similarly with inverted voltages and cur-
rents. The drain current is modulated by the voltage differences between the three device
electrodes drain (D), gate (G), and source (S). In principle, an OFET operates as a voltage-
dependent resistor between drain and source which is controlled by the gate-source and drain-
source voltage. In logic circuits, this resistor can be regarded as a nonlinear switching element
which cannot be completely switched-off as shown by the logarithmic transfer characteristics
in Fig. 2.2c.
0 0
VDS
VDS
D
G
S
ID
VGS
VGS
fixedVDS
VGS1
VGS2
VGS3
VGS4
b)a) c)
ID log ID
Fig. 2.2: a) FET symbol with terminal voltages and drain current, b) schematic output char-acteristicsID vs. VDS, and c) logarithmic transfer characteristicsID vs. VGS.
12 Chapter 2. Concepts of Low-Cost Organic Electronics
In OFETs, the drain currentID is usually proportional to certain material and structural
properties. These material properties are charge-carriermobility µ or the relative permittivity
εr of the insulator capacitance. Structural properties are channel widthW , channel length
L, or the thickness of the insulating layertis. Using these parameters,ID (here again dis-
cussed for an n-type device) can be approximated by the well-known Shichman-Hodges [15]
equations
ID =
WL
µCis
[
(VGS − VT )VDS − 12V 2
DS
]
: VDS < VGS − VT
12
WL
µCis(VGS − VT )2 : VDS > VGS − VT
(2.1)
The voltagesVDS andVGS are defined according to Fig. 2.2.VT is the threshold voltage.
It can roughly be defined as the voltage at which the channel begins to switch on.Cis is the
capacitance per unit area of the insulator and readsCis = ε0εr/tis. ID saturates at highVDS
values (|VDS| ≥ |VGS − VT |) because the voltage drop across the channel no longer leadsto
accumulation of charge carriers. In a first-order approximation, the channel region there is
regarded as being pinched-off. Consequently, the drain current saturates.
OFETs belong to the class of thin-film transistors where the semiconducting channel is
deposited as a thin film on the substrate. Owing to this fact, OFETs are also referred to as
OTFTs (Organic Thin-Film Transistors, e.g. [9]). Fig. 2.3 shows a graphical representation of
frequently used OFET structures. These structures are distinguished according to the positions
of the electrodes. In top-gate structures, the gate electrode is deposited on top of all other
layers. In bottom-gate structures, conversely, it is deposited first on the substrate. Each device
setup has special requirements on the compatibility between the different materials used in
the fabrication process (layer materials, solvents, resists, developers).
Top-gate devices provide the advantage of encapsulating the semiconducting layer be-
tween the substrate and the insulator. Bottom-gate devicesare often fabricated using the
well-established technology of silicon wafers. Silicon isused for the gate electrode while
silicon dioxide grown on top of the silicon acts as the insulating layer [16].
Charge-carrier mobilities of amorphous organic transistors are usually very low, i.e. in
the rangeµ < 0.1 cm2/Vs [17] as opposed to crystalline silicon transistors withelectron mo-
bilities µ > 500 cm2/Vs. This restriction leads to OFETs with large channel widths in the
millimeter range so to allow drain currents of 1µA and above. Therefore, OFETs are often
realized as interdigitated structures. Fig. 2.4 shows an OFET (top-gate structure) with five fin-
gers in top view. The geometrical device parameters (channel length and width) are indicated
in the drawing.
Parameters for fully-printed as well as clean-room fabricated devices are given in Table 2.1.
For the printed devices, the semiconductor was PTAA while the clean-room fabricated devices
2.3. Organic Field-Effect Transistors 13
Semiconductor
Drain Source
Insulator
Substrate
Gate
Semiconductor
Insulator
Gate
Substrate
Drain SourceGate
SourceDrain
Insulator
Substrate
Semicon.
b) Bottom–gate bottom–contact c) Bottom–gate top–contacta) Top–gate
Fig. 2.3: Schematic view of different OFET classes: a) top-gate structure, b) bottom-gatebottom-contact structure, and c) bottom-gate top-contactstructure.
Gate
SourceDrain
Channel widthW
Channel lengthL
Fig. 2.4: Schematic top view of an OFET with an interdigitated finger structure.
was manufactured using P3HT. As can be seen from the listed data, considerable differences
between the two processes exist.
Table 2.1: Parameters for fully-printed [18] and clean-room fabricated [19] OFETs.Parameter fully-printed clean-room fabricated
relative insulator permittivityεr 2.2 to 50 3insulator thicknesstis 0.1-10µm, depends onεr 300 nmelectrode thickness > 300 nm 40 nmsemiconductor thickness > 500 nm 50 nm
2.3.2 Differences between MOSFET and OFET
In the following, the operation modes of MOSFETs and OFETs will be compared. First, the
well-known MOSFET is shortly presented and is then comparedwith an OFET in order to
show the differences between the two transistor types. P-type transistors will be used in the
discussion.
14 Chapter 2. Concepts of Low-Cost Organic Electronics
MOSFET Operation
In p-type MOSFET devices, the channel region is a substrate with n-type doping, i.e. with
electrons as majority carriers (see Fig. 2.5). An oxide is grown on top of the channel region
and serves as the insulator. The drain and source region are both p-type doped with holes as
majority carriers. Therefore, there exist pn junctions at the interface between the electrodes
and the channel when zero voltages are applied at drain, gate, and source. By applying a
negative voltage between gate and source, the channel is depleted. WhenVGS reaches the
threshold voltageVT , the concentration of minority carriers (holes) begins to exceed the con-
centration of majority carriers (electrons) and the deviceoperates in inversion mode where
the channel region is p-type conducting. Under these conditions, the pn junctions between the
source electrode and the channel as well as the drain electrode and the channel no longer exist
and current can flow between drain and source through the channel. By applying a positive
VGS, majority carriers (electrons) are accumulated and the channel is switched off. No mat-
ter which polarityVDS has, always one of the two pn diodes at source and drain is biased in
reverse direction and blocks current flow.
Drain Sourcep+ p+
n−Substrate
Gate Oxide
Gate
Fig. 2.5: Schematic cross section of a p-type MOSFET (p+ and n+ denote heavily p-type andheavily n-type doped regions).
OFET Operation
In a p-type OFET, the semiconducting channel is deposited asa thin film on an insulating
substrate or the dielectric. The semiconductor is not dopedbut intrinsically provides hole
transport. Source and drain electrodes are metals or metal-like conductors with (ideally) little
resistance to the channel region for transport of holes. By applying a negativeVGS, holes
injected from the source electrode are accumulated in the channel. Conversely, a positiveVGS
depletes the channel and leads to higher channel resistance, which leads to low current.
2.4. Printing and Roll-to-Roll Fabrication 15
Comparison
Table 2.2 provides a comparison between silicon-based MOSFET and OFET technologies.
Table 2.2: Comparison between silicon-based MOSFET and OFET technologies.Property MOSFET OFET
Operation mode strong inversion accumulationTransport mechanism band transport various models, but still
under debateSource/drain contacts pn junctions for majority
carriers, one of these is re-verse biased
low-resistance contacts formajority carriers
Substrate provides channel region,semiconducting
no electric function, insu-lating
Typical Charge-carriermobility
400 to 500 cm2/Vs forelectrons
≤ 0.1 cm2/Vs in amor-phous semiconductors
Fabrication method lithographic process, usingclean-room facilities
various, from photolitho-graphy to printing
Semiconductor silicon various conjugated poly-mers/oligomers
Insulator mainly silicon dioxide numerous possibilitiesElectrodes / Intercon-nect
various metals, polysilicon(as gate)
various metals and organicconductors
Critical dimension < 1 µm > 1 µm
2.4 Printing and Roll-to-Roll Fabrication
Based on the selection of constituent materials, OFET-based circuits can be fabricated in
a variety of deposition (e.g. vapor deposition, spin-coating) and structuring methods (e.g.
photolithography, shadow masks). The reader is referred to[20, 21] for a review of fabrication
techniques used in organic electronics.
The most advantageous fabrication techniques are printingmethods, which are not appli-
cable in conventional silicon-based processes. Printing techniques like flexography, gravure
printing, screen printing, or inkjet printing, etc. can be used. These lead to high fabrication
volume and throughput as well as low-cost fabrication, which are specific features of low-cost
organic electronics.
Use of printing techniques comes at the cost of some restrictions. The feature sizes are
currently limited to the micrometer range instead of a nanometer scale used with conventional
16 Chapter 2. Concepts of Low-Cost Organic Electronics
silicon transistors [18]. Printing materials have to be chosen carefully so to remain compatible
with the respective printing technology regarding e.g. viscosity, drying behavior, etc. [21, 22].
Some printing techniques can be used inroll-to-roll manufacturing, where the printing
substrate is fed through a printing machine from one roller to another. In comparison to batch
processing of IC wafers, roll-to-roll manufacturing can reach higher throughput. In order to
explain roll-to-roll manufacturing, gravure printing will be discussed in the following with the
help of Fig. 2.6. In gravure printing, a flexible foil is continuously unwound from a roll, travels
between a rotating gravure cylinder and an impression cylinder, and is finally rewound into
another roll. In the printing process, the surface of the rotating gravure cylinder is wetted by
an ink or soluble polymer in a tank. The ink (in organic electronics: semiconductor, insulator,
metal-like electrode material, etc.) is scraped by a doctorblade so that only the quantity filling
up the recessed parts of the cylinder remains. This ink is transferred to the desired positions
of the printing substrate while the cylinder rolls across it.
Printing substrate
Gravure cylinder
Ink
Impressioncylinder
Roll
Roll
Doctor blade
Fig. 2.6: Schematic gravure printing process (adaption from [23]).
2.5. Chapter Conclusions 17
2.5 Chapter Conclusions
As was shown in Section 2.3.1, MOSFETs and OFETs operate similarly. From the modeling
point of view, the two types of transistors differ in operation mode (strong inversion vs. accu-
mulation), transport mechanisms (band transport vs. various possibilities from band transport
to hopping), and technological choices (materials, fabrication methods). Yet, output and trans-
fer characteristics are comparable. Therefore, MOSFET-based models of transistors are used
as first-order approximations of OFETs in circuit simulation. Nevertheless, the OFET tech-
nology features numerous fabrication methods and materials for the various transistor layers.
This situation creates many factors complicating modelingbecause different transport mech-
anisms (band-like, hopping) and effects at the interfaces between the semiconductor and the
electrodes (presence of contact effects) or between the semiconductor and the insulating layer
(presence of traps, hysteresis) might arise. Hence, a generic simulation environment needs to
adapt to different modeling approaches and procedures for parameter extraction.
18 Chapter 2. Concepts of Low-Cost Organic Electronics
19
Chapter 3
OFET Modeling for Circuit Simulation
Circuit simulations of low-cost organic circuits are useful in the development and optimization
of devices and processes. Simulations provide relevant performance figures during device
optimization. They can be used without fabricating and measuring real devices. However,
employing circuit simulation in this field requires accurate OFET models.
This chapter discusses models suitable for circuit simulation as well as procedures and
tools for extracting the respective model parameters. First, requirements are defined which
determine the strengths and weaknesses of transistor models. These requirements are useful
when comparing models and identifying their deficiencies. Next, existing OFET models pre-
sented in literature on device modeling are discussed. Finally, frequently used procedures and
tools for the extraction of transistor parameters are reviewed.
3.1 Model Requirements for Circuit Simulation
Transistor models need some properties in order to be usefulin the simulation of OFET-
based logic circuits. Model performance in digital circuits usually depends on a small set
of parameters of the DC characteristics such as threshold voltage and drive current [24]. A
“good” agreement betweenID-VDS measurements and simulation is traditionally considered
to be enough [25]. The level of accuracy can be defined by the mean-square error between
measurement and simulation [25, 26, 27]. However, users of transistor models prefer more
sophisticated rating criteria in order to identify the strengths and weaknesses of individual
models. Tsividis and Suyama [25] studied requirements on transistor models useful in the
simulation of circuits. Their research focused on model requirements for analog circuits but
the results can also be adapted to models for OFET-based digital circuits. In this work, the
idea of Tsividis and Suyama is adapted to the assessment of OFET devices. The adaption
consists of grouping the requirements into five sections, dropping criteria more important for
20 Chapter 3. OFET Modeling for Circuit Simulation
analog models, and adding new criteria dealing with the accuracy of predicted voltage levels,
noise margin, or stress effects. Good candidates for modeling OFET devices should comply
with as many requirements as possible of the followingmodel quality chart(MQC):
2 Accuracy— A candidate model should give reasonably accurate resultsfor
⊲ I-V characteristics,
⊲ speed predictions for logic circuits,
⊲ propagation delays at the individual nodes within the circuit,
⊲ voltage levels and noise margin determinations,
⊲ a reasonable range of bias voltages and temperatures.
2 Capacitance Modeling— The model should include proper modeling of the transistor
capacitances like gate-source and gate-drain capacitances. The accurate simulation of
time-dependent voltage levels and signal shapes depends onthe correct modeling of
these capacitances.
2 Compactness— The model equations should depend on as few parameters as possible:
⊲ There should be a strong relationship between model parameters and parameters
reflecting device structure and fabrication processing (channel thickness, number
of trap states, etc.).
⊲ Such a model would be especially useful in statistical circuit analysis where effects
of variations in fabrication and parameter distribution are accounted for.
⊲ In order to be of service in statistical circuit analysis, empirical parameters without
physical meaning should be avoided.
⊲ The model accuracy should not depend on the geometrical dimensions of each
device, so one set of model parameters should be valid for alldevices of the same
type and fabrication process.
2 Parameter Extraction— The process of parameter extraction must be easy and straight-
forward:
⊲ The number of required test devices and measurement procedures for the parame-
ter extraction should be kept as small as possible.
⊲ Ideally, model parameters are directly resolved using analytical reasoning without
much computational effort.
3.2. Existing Models for OFETs 21
⊲ Alternatively, if general-purpose optimization techniques are used, they must not
fail due to numerical instabilities.
2 Stress Effects— The candidate model should implement hysteresis effects present in
OFET devices like the threshold voltage shift due to bias stress [3, 28, 29, 30].
Although OFET-based modeling does currently not meet all ofthe above requirements,
the MQC is a useful tool in the discussion of strengths and weaknesses of different model-
ing approaches. Currently, the following issues prevent complete compliance with the MQC
criteria:
2 The physics of OFETs are not fully understood yet. Experiments presented in literature
are often carried out on devices fabricated on silicon wafers and by photolithographic
means. Such devices are not comparable to devices fabricated with low-cost manufac-
turing techniques. For the latter, fabrication speed and cost are more important than
device quality and repeatability.
2 Devices consist of nonuniform and complicated materials. This contrasts modeling
of crystalline silicon transistors made of uniform and well-characterized materials [31].
Under these circumstances, deriving a small set of physics-related parameters is difficult
and often leads to empirical modeling of the devices.
2 OFETs can be fabricated using a variety of device structuresand fabrication processes.
This situation gives rise to many individual effects. One example of such effects is the
series resistance between the electrodes and the transistor channel. Depending on the
device structure, the series resistance influences the transistor current [28, 32]. A large
variety of candidate materials for the semiconductor, the dielectric, and the interconnect
lines also leads to additional variables in the modeling process.
3.2 Existing Models for OFETs
In the following, transistor models are presented which have already been applied to OFETs.
Some of these models were developed for more traditional semiconductor materials while
others are especially designed for specific types of OFETs. The following review makes
use of the model quality chart (MQC) in order to compare weaknesses and strengths of the
individual models. However, the reader should note that themodels are difficult to compare
regarding accuracy as they have been developed for different device setups, i.e. different
material combinations, device structures, and fabrication methods.
22 Chapter 3. OFET Modeling for Circuit Simulation
The models reviewed in the following sections can roughly bedivided into different cate-
gories. These categories are:
1. Models adapting well-known approaches for silicon transistors based on the shapes
of the output characteristics or structural similarities (Level-1 in Section 3.2.1, TFT
models in Section 3.2.2 and Section 3.2.3).
2. A model specifically developed for OFETs, i.e. the model ofvariable range hopping
(VRH) in four variants in Section 3.2.4.
3. Models sacrificing any physical background (table-basedmodels in Section 3.2.5, Dres-
den model in Section 3.2.6) but instead focusing on quick andaccurate reproduction of
measured output characteristics.
4. Models for ambipolar OFETs in Section 3.2.8, which are combinations of other models.
A special situation arises from Necliudov’s [32] application of the TFT model for amor-
phous silicon to OFETs (Section 3.2.3). Here, the generic adaption of a silicon-based model
is combined with OFET-specific contact effects. Brederlow and colleagues [33] developed a
similar approach but focused on a physics-related description of the contact effect and mod-
eled the intrinsic transistor with standard MOSFET equations. In this work, the model in [33]
has nevertheless been listed in the section dealing with theTFT model for amorphous silicon
as the model description was too short for a thorough analysis within the framework of this
thesis.
3.2.1 Shichman-Hodges Model (Level-1 Model)
A popular and simple transistor model was developed by Shichman & and Hodges in the 1960s
for the general class of IGFETs (insulated gate field-effecttransistors) [15]. In the following,
the name “Level-1 model” will also be used for this approach.The name originates from
SPICE, where Shichman-Hodges modeling is selected for MOSFETs by setting the transistor
parameter LEVEL=1 [34].
Some researchers employ the Level-1 equations as a first-order approximation of the out-
put characteristics of OFETs (e.g. [3, 35]). The equations are also used in Section 2.3.1 for a
discussion of the electrical behavior of OFETs.
Although the Level-1 model has been developed with operation in strong inversion mode
in mind, the resulting current-voltage relationship also approximates thin-film transistors op-
erating in accumulation mode as has been shown in [36].
3.2. Existing Models for OFETs 23
3.2.1.1 Model Equations
Fig. 3.1a shows the output characteristics of an OFET, whichcan be divided into three regions:
cutoff (not visible in the plot),linear, andsaturation. In the following text, equations for the
three regions will be presented by use of an n-type transistor but the resulting equations are
applicable to both n-type and p-type devices.
For an n-type transistor with true Level-1 behavior, no current flows forVGS less than the
threshold voltageVT . The device is then in the cut-off region (see Fig. 3.1b). Above threshold,
the current increases with a square-law dependence onVDS in the linear region until it reaches
the boundary between linear and saturation region (shown bythe dotted line in Fig. 3.1a). In
the saturation region, the current is proportional to the drain-source voltage.
a) Output characteristics b) Transfer characteristics
Linear Region Saturation Region
CutoffRegion Region
SaturationRegionLinear
0 0
VDS = VGS − VT
VGS ↑
VT
ID ID
VDS VGS
VDS = const
Fig. 3.1: Schematic output characteristics of a transistorwith Level-1 behavior: a) outputcharacteristicsID vs. VDS with linear and saturation region separated by a dotted curve, andb) linear transfer characteristicID vs. VGS with threshold voltageVT .
The equations of Level-1 transistors were already introduced in (2.1) but will be repro-
duced here in order to separate the different operation regions:
1. Cutoff region:
ID = 0 with VGS < VT (3.1)
2. Linear region:
ID = µ·Cis·W
L
(
VGS − VT − VDS
2
)
VDS·(1+λVDS) with 0 < VDS < VGS−VT (3.2)
24 Chapter 3. OFET Modeling for Circuit Simulation
3. Saturation region:
ID =1
2µ · Cis ·
W
L(VGS − VT )2 · (1 + λVDS) with 0 < VGS − VT < VDS (3.3)
The parameters used in (3.1) to (3.3) areµ for the charge-carrier mobility,Cis for the
capacitance per unit area of the gate dielectric,VT for the threshold voltage,λ for the channel-
length modulation parameter,W andL for the width and length of the transistor channel. For
convenience reasons in hand calculations, the process conductance parameterKP [37] was
introduced as
KP = µCis. (3.4)
The device conductance parameterβ further extendsKP by taking into account the geometry
of the transistor. It is defined as
β = KPW
L= µCis
W
L. (3.5)
The process conductance parameterKP reflects the driving capabilities of the transistor
device. The threshold voltage on the other hand defines how much gate-source voltage is
needed to induce charge carriers in the transistor channel.The channel-length modulation
parameter has been introduced in the original IGFET equations to account for a channel-
length reduction in saturation. This reduction is associated with the pinch-off of the transistor
channel at some point near the drain electrode. The pinch-off leads to a reduction of the
effective channel length which in turn increases the slope of ID vs. VDS in the saturation
region. The value ofλ defines this slope according to (3.3).λ = 0 corresponds to a slope of
zero in the saturation region.
Reasonable parameter values for Level-1 devices are given in Table 3.1. As there is not just
one mainstream OFET technology but many different processes currently in the development
stage, parameter values for the various fabrication technologies considerably differ. Therefore,
it is not possible to provide typical values, and Table 3.1 can only provide a general idea of
reasonable parameter ranges.
Table 3.1: Level-1 parameters for p-type P3HT device [19].Parameter Value
process conductanceKP < 9 pA/V2
threshold voltageVT 0,2 Vchannel-length modulationλ 5 · 10−3 1/V
The influence of Level-1 parameters on modeled output characteristics is demonstrated
using Fig. 3.2, where output and transfer characteristics of variations of all three Level-1 pa-
3.2. Existing Models for OFETs 25
rameters are shown. The reference device was an n-type FET with the following parameters:
KP = 1 nA/V2, VT = 2 V, λ = 0, W/L = 2000. The parameters have been chosen for demon-
stration purposes. In Fig. 3.2a-b, the effect of varying theprocess conductance is depicted.
IncreasingKP from 1 pA/V2 to 1.5 pA/V2 will proportionally increase the drain currentID.
In Fig. 3.2c-d, the influence of the threshold voltage is demonstrated. Here,VT is raised
from 2 V to 10 V. The impact of this increase is best seen in theID vs. VGS plot where
the onset of drain current shifts fromVGS = 2 V to 10 V. In Fig. 3.2e-f, the impact of the
channel-length modulationλ is shown.
3.2.1.2 Discussion
In Table 3.2, a rating of Level-1 modeling with respect to themodel quality chart (MQC)
from Section 3.1 is shown. Due to the multitude of materials and processing routes, there is
no uniform shape of the current/voltage characteristics ofOFET devices [30]. Therefore, the
accuracy of the Level-1 approach has been rated from bad to medium. It can adequately repro-
duce OFET types where the mobility only weakly depends on thegate-source voltage. Other
modeling approaches are better suited for devices with e.g.variable mobility. Modeling of
capacitances is not part of the basic equations. It should benoted, however, that Level-1 imple-
mentations in SPICE simulators include nonlinear modelingof capacitances which is similar
to OFET-related capacitance values expectable from numerical analysis (see Section 3.2.4.2).
As the Level-1 model is based on a physical background (gradual channel approxima-
tion) and only few parameters are necessary in the equations, compactness of the model has
been rated as good. Numerous approaches can be used for deriving these parameters (see
Section 3.3.1). Therefore, parameter extraction has also been rated as good. Stress effects are
not included in the model.
Table 3.2: MQC for basic Level-1 model.Requirement Rating
Accuracy bad to mediumCapacitance Modeling not includedCompactness goodParameter Extraction goodStress Effects not included
In literature on modern MOSFET modeling [38], the Level-1 approach is only considered
as a convenient first-order approximation because the relatively simple equations facilitate
parameter extraction. More advanced models require concurrent fitting of several parameters
to more sophisticated equations, which complicates the extraction process.
26 Chapter 3. OFET Modeling for Circuit Simulation
f)
d)
b)a)
e)
c)
0.0u
0.5u
1.0u
1.5u
2.0u
2.5u
3.0u
3.5u
−10 0 10 20 30 40 50
0.0
0.5u
1.0u
1.5u
2.0u
−10 0 10 20 30 40 50
0.0u
0.5u
1.0u
1.5u
2.0u
2.5u
0 10 20 30 40 50
0.0u
0.5u
1.0u
1.5u
2.0u
2.5u
3.0u
3.5u
0 10 20 30 40 50
0.0u
0.5u
1.0u
1.5u
2.0u
0 10 20 30 40 50
30 40 50
80n
70n
60n
50n
40n
30n
20n
10n
0n 0 10 20
I D[A
]I D
[A]
I D[A
]I D
[A]
I D[A
]
I D[A
]
VGS [V]
VGS [V]
VGS [V]
λ = 0.000 1/V
VT = 2 V
VDS = 50 V
VDS = 50 V
VDS = 50 V
KP =1.5 pA/V2
VT = 10 V
λ = 0.005 1V
KP =1.0 pA/V2
VDS [V]
VDS [V]
VT = 2 V
λ = 0.005 1/Vλ = 0.000 1/V
VGS = 50 V
40 V
20 V
30 V
VGS = 10 V
VT = 10 V
KP =1.0 pA/V2
KP =1.5 pA/V2
VDS [V]
Fig. 3.2: ID vs. VDS andID vs. VGS for variations of the Level-1 parameters: a-b) variationof KP , c-d) variation ofVT , and e-f) variation ofλ.
3.2. Existing Models for OFETs 27
3.2.2 Model for Polycrystalline TFTs
The Level-1 model presented in Section 3.2.1 was designed for crystalline silicon transistors
and does not account forVGS-dependent mobilities. Therefore, more sophisticated modeling
approaches for organic transistors have been presented in literature such as the grain bound-
ary model for polycrystalline transistors. This model is based on the fact that vapor-deposited
organic semiconductors like pentacene organize themselves into grains of single-crystalline
structure [39]. Charge carriers are impeded by traps when they move across boundaries of
adjacent grains. Those traps can cause carrier scattering and momentum transfer to phonons
in the crystal [39]. The existence of traps leads to trappingof carriers, which in turn is re-
sponsible for a depletion of charge carriers at the grain boundaries [40] and the formation of
a barrier potential.
Polycrystalline silicon thin-film transistors (Psi-TFTs)show comparable behavior. In
these devices, the mobility is described by an empirical equation
1
µeff=
1
µg+
1
µgb, (3.6)
with µeff being the effective mobility (i.e. net mobility),µg the mobility inside the single-
crystalline grain, andµgb the mobility obtained at the grain boundaries.
The drain current above threshold can be calculated with
Id =W
L
VDS∫
0
Cis [VGS − VT − V (x)] · µeff dV, (3.7)
whereV (x) is the drain-source voltage at positionx along the length of the channel. The
other variables have their usual meaning.
Popular simulation models for polycrystalline silicon do not provide an exact solution to
(3.7) but instead express the mobility by an empirical equation, e.g. [41] for the Psi-TFT
model from the Rensselaer Polytechnic Institute (RPI, Troy, NJ, USA). Such an approach
eventually leads to an adaption of the basic model presentedin Section 3.2.1 with aVGS-
dependent mobility [42]. The nature of charge transport in organic semiconductors is still a
matter of debate. Nonetheless, some groups (e.g. Horowitz and co-workers [43], Frisbie and
co-workers [44, 45]) established theories for organic crystals and polycrystalline structures
where charge transport within a single grain can be viewed asband-like. Transport across
grain boundaries and the semiconductor interface to the electrodes, however, is impeded by
the presence of traps.
The Psi-TFT model has been used in [46] for modeling of the above-threshold current of
OFETs.
28 Chapter 3. OFET Modeling for Circuit Simulation
3.2.2.1 Model Equations
In the following, simplified equations for the RPI Psi-TFT model will be presented. A more
detailed description can be found in [47]. The RPI model assumes the effective charge-carrier
mobility µeff to be determined by an empirical law
1
µeff=
1
µ′
1
+1
µ0, (3.8)
with µ0 being an upper mobility limit for high gate biases similar toµg in (3.6) andµ′
1 deter-
mined by an empirical power law for lowVGS values as
µ′
1 ∼ µ1Vmµ
GST . (3.9)
Here,µ1 is the low-field mobility andmµ is a mobility parameter. Both quantities can be
extracted from current-voltage measurements. For convenience reasons,VGST = VGS − VT is
used.
The drain current is composed of three contributors:
1. the subthreshold leakage currentIleak,
2. the subthreshold currentIsub,
3. the above threshold currentIa.
Fig. 3.3 shows a schematic plot1 of the drain current and its three contributors in logarith-
mic scale vs. the gate-source voltageVGS. The derivation of the equations forIleak, Isub, and
Ia are detailed by Jacunski and colleagues [47]. In this work, only simplified equations will
be presented in order to show theVGS- andVDS-dependence of the contributing currents.
The subthreshold leakage currentIleak in the RPI model has not been used in the modeling
of OFETs so far. Therefore, the equations will not be reproduced here.
The subthreshold current in the Psi-TFT model reads
Isub = µs · CisW
L(ηiVth)
2 exp
(
VGST
ηiVth
)[
1 − exp
(−VDS
ηiVth
)]
. (3.10)
Here,µs is the subthreshold mobility andηi is the subthreshold ideality factor. Both param-
eters are extracted using measurements of the drain current. The other parameters have their
usual meaning.
1Model data:µeff = 1 · 10−3 cm2/Vs, Cis = 1 · 10−7 F/cm2, VT = 1 V, αsat = 1.1, µs = 1 · 10−11 cm2/Vs,ηi=3.34,I0 = 1 · 10−13 A, W/L = 1000. A simple fitting equation for the leakage current has been used, whichreadsIleak = I0 exp(−(VGS − VT )/6).
3.2. Existing Models for OFETs 29
10.0f
100.0f
1.0p
10.0p
100.0p
1.0n
10.0n
100.0n
1.0u
10.0u
−4 −2 0 2 4 6 8 10
VGS [V]
Ia
Isub
Ileak
I D[A
]
Fig. 3.3: Operation regions of a simulated Psi-TFT.
The slope of the subthreshold currentIsub in (3.10) in decimal logarithmic scale is given by
log e/(ηiVth). For OFETs, it is the reciprocal of the subthreshold swing [48] or subthreshold
slope [49]S. [49] defines thesubthreshold slopeas the necessary variation of the gate-source
voltage for modulating the subthreshold current by one decade. Alternatively, the IEEE stan-
dard on the characterization of OFETs [48] defines thesubthreshold swingas the maximum
slope of the logarithmic transfer characteristic in the subthreshold region. The subthreshold
slope is given in V/dec and typically ranges from 1 to 5 V/dec for p-type organic semicon-
ductors [49]. In comparison to crystalline silicon with a typical subthreshold slope of approx-
imately 60 mV/dec at room temperature, a large range of gate-source voltage is required to
achieve low off currents [49].
The above-threshold drain currentIa is given by [26]
Ia =
µeffCisWL
(
VGST VDS − V 2
DS
2αsat
)
for VDS < αsat(VGST )
µeffCisWL
(VGST )2αsat
2 for VDS ≥ αsat(VGST )
(3.11)
Here,µeff is theVGS-dependent mobility from (3.8),αsat is an empirical parameter accounting
for a VGS-dependent modulation of the transition point between the linear and the saturation
region.
30 Chapter 3. OFET Modeling for Circuit Simulation
The total drain current is calculated by
ID = Ileak +1
1
Isub+
1
Ia
. (3.12)
With the reciprocal subterm, a unified equation for the subthreshold region, above-threshold
region and transition region between the two can be used.
The effective control voltageVGST used in the RPI model is defined by
VGST =
VGS − VT for VGS − VT > 2ηiVth
2ηiVth else
. (3.13)
Hereηi is the subthreshold ideality factor introduced in (3.10). (3.13) effectively limits
VGST to values above2ηiVth. Without limitingVGST , values close to zero could be reached in
(3.11). These values would introduce an incorrect singularity in the transition region.
A reasonable parameter set for a P3HT transistor in top-gateconfiguration is listed in
Table 3.3 (details on how the values were obtained are given in Section 4.3.6).
Fig. 3.4 provides plots where the parametersmµ andαsat are varied. Reference parameters
for the plots wereαsat = 1.0, mµ = 0.0, VT = 2.0 V. These were chosen so that the drain
currents of the Psi-TFT device and the Level-1 device presented in Section 3.2.1 are identical.
By varyingαsat andmµ, the changes introduced by the Psi-TFT equations with respect to the
original Level-1 modeling can be studied.
3.2.2.2 Discussion
A rating of the polycrystalline grain boundary model is presented in Table 3.4. The model
takes aVGS-dependent mobility into account. Therefore, accuracy hasbeen rated as good (see
Section 4.3.6 for an example of model accuracy). Modeling ofcapacitances is not included
in the model. Compactness has been rated as good because onlya small number of parame-
ters is needed for modeling the above-threshold behavior. One can argue, however, that the
underlying RPI model uses only an “effective medium approach” [50] where the stochastic ar-
rangement of grains of different sizes is modeled by a singleeffective medium with equivalent
properties. Hence, the model equations can be considered asstatistical descriptions. This fact
complicates finding the relationship between model parameters and those parameters which
reflect device structure and fabrication processes. Nevertheless, compactness has been rated
as good as only a small amount of parameters is necessary. Parameter extraction is difficult
because of the bias-dependent mobility as will be discussedin Section 3.3.2. This property
leads to a rating of medium. Similar to Level-1 modeling, stress effects are not included in
3.2. Existing Models for OFETs 31
Table 3.3: Psi-TFT parameters for top-gate p-type P3HT device (other parameters not used).Parameter Value
capacitanceCis per unit area 1 · 10−7 F/cm2
low-field mobility µ1 2.5 · 10−5 cm2/Vszero-bias threshold voltageVT 2.9 Vsaturation variation parameterαsat 0.8low-field mobility exponentmµ 0.886channel-length modulation parameterλ 0.005 V−1
b)
d)
a)
c)
1.5u
0 10 20 30 40 50
0 10 20 30 40 50
2.0u
1.0u
0.5u
0.0u
4.0u
3.5u
3.0u
2.5u
2.0u
1.5u
0.5u
1.0u
0.0u
0 10 20 30 40 50
0 10 20 30 40 50
4.0u
3.5u
3.0u
2.5u
2.0u
1.5u
1.0u
0.5u
0.0u
2.0u
1.5u
1.0u
0.5u
0.0u
I D[A
]
I D[A
]I D
[A]
I D[A
]
VDS [V]
αsat = 1.0
VDS [V]
αsat = 0.5
mµ = 0.0mµ = 0.1
VGS [V]
αsat = 1.0
VGS [V]
αsat = 0.5
mµ = 0.1mµ = 0.0
Fig. 3.4: ID vs. VDS andID vs. VGS for variations of the Psi-TFT parametersαsat andmµ:a-b) variation ofαsat, c-d) variation ofmµ.
32 Chapter 3. OFET Modeling for Circuit Simulation
the model.
Table 3.4: MQC for Psi-TFT.Requirement Rating
Accuracy goodCapacitance Modeling not includedCompactness goodParameter Extraction mediumStress Effects not included
The effective medium approach has also been used for studying the grain-size-dependent
mobility for pentacene-based OFETs [51] in order to yield aneffective mobility
µeff = µg1
1 + nβ exp(qVB/kT ), (3.14)
with µg being the grain intrinsic mobility,n the number of grain boundaries along the chan-
nel,β the ratio between an effective grain-boundary size and the channel length, andVB the
potential barrier between grains. For polycrystalline silicon TFT (Psi-TFT) devices, similar
relationships have been exploited to derive closed-form drain-current equations in the form of
[52]
ID =W
LµeffCis(VGS − VT )VD. (3.15)
Here, the drain current in the linear region is modeled. Results in [51] suggest thatµeff non-
linearly depends on the effective grain size and the gate-source voltage. Studies on theVGS
dependence of Psi-TFT devices in [52] yielded a sixth-orderpolynomial needed for modeling
of the potential barrierVB(VGS). To the knowledge of the author of this work, this model
has not been applied to polycrystalline OFETs so far. It is suggested to further explore this
approach.
3.2.3 Model for Amorphous TFTs
Necliudov and colleagues [32] describe a model which improves the fitting between the Level-
1 model and experimental data for vapor-deposited pentacene OFETs. The model is based on
the assumption that above threshold, most of the charge carriers induced in the channel are
trapped and only a small fraction contributes to charge transport. AVGS-dependent mobility
reflects this property. The model is derived from the TFT model for amorphous silicon TFTs
(a-Si TFT). In a-Si TFTs, no long-range order of the silicon material exists. Instead, the atoms
are organized in a random network, which leads to many energystates in the forbidden band-
gap. These states are localized and statistically distributed. They arise from unterminated
3.2. Existing Models for OFETs 33
bonds or variations of bond angle and bond length. Fig. 3.5 provides a schematic view of
the energy band diagrams of crystalline and amorphous silicon. In crystalline silicon, there is
a clear band gap without states between the edges of the valence band (EV ) and conduction
band(EC). In amorphous silicon, no clearly-defined band gap exists.
bandbandvalence conduction
band bandvalence conduction
dens
ity o
f sta
tes
energy
energy
dens
ity o
f sta
tes
a) crystalline
b) amorphous
stateslocalized
forbiddenband gap
EV EC
ECEV
Fig. 3.5: Schematic energy band diagram of a) crystalline silicon and b) amorphous silicon(adaption from [53]).
Charge carriers trapped in band-gap states do not contribute to the drain current of the
FET. Hence, the effective mobility of a-Si TFTs is below the one of single-crystalline silicon
devices. Moreover, it depends on the gate voltage because athigher gate voltages, more trap
states are filled and therefore, more charge carriers of the ones injected at the source electrode
can contribute to the current flow.
3.2.3.1 Model Equations
The gate-voltage dependent mobilityµ is described by a fitting function as
µ = µ0
(
VGS − VT
VAA
)γ
. (3.16)
Here,µ0, VAA, andγ are fitting parameters obtained from experimental data, where γ is a
power parameter andVAA is the characteristic voltage for the charge-carrier mobility [54].
34 Chapter 3. OFET Modeling for Circuit Simulation
[32] reported results for top-contact (TC) and bottom-contact (BC) pentacene devices.
Bottom-contact devices showed nonlinear output characteristics at gate-source voltages around
zero. These devices were modeled with constant source and drain series resistors and pairs of
Schottky diodes. Fig. 3.6 shows the configuration. The approach is an adaption of the RPI
model for amorphous silicon thin-film transistors (RPI a-SiTFT) [55] to organic transistors.
It is a fitting model which neglects the physical background of the equations.
S
RS
RD
G
D
Fig. 3.6: Equivalent circuit of a bottom-contact OFET with diodes and series resistors formodeling non-linear contact resistance.
The Schottky diodes are modeled with an empirical extensionto the basic Shockley equa-
tion. The extension introduces an ideality factorη which accounts for the influence of non-
ideal effects (η > 1) on the diode current [50]. This currentI is
I = IS
[
exp
(
V
ηVth
)
− 1
]
. (3.17)
Here,IS is the saturation current,V the voltage drop across the diode, andVth is the thermal
voltage.η determines the steepness of the I-V characteristic of (3.17).
3.2. Existing Models for OFETs 35
3.2.3.2 Experimental Extraction Results
Necliudov and colleagues obtained contact resistances in the range of 50 kΩ to 100 kΩ for
channel widths of 220µm and a diode ideality factorη = 10 for a pentacene device with bot-
tom contacts. Detailed information on the parameters necessary for calculating the saturation
current is not given in [32]. Nevertheless, adequate extraction procedures for standard a-Si
TFTs are available e.g. in in [56, 57].
Table 3.5 provides model parameters for pentacene devices fabricated in both bottom-gate
top-contact (TC) and bottom-gate bottom-contact (BC) configuration [32].
Table 3.5: Typical model parameters of top-contact (TC) andbottom-contact (BC) pentaceneOFETs [32].
Type W/L RS,D VT µ0 γ VAA η
TC 220µm /30µm 100 kΩ 5 V 10 cm2/Vs 0.45 300 kV -BC 220µm /20µm 50 kΩ 13 V 10 cm2/Vs 0.38 19 kV 10
3.2.3.3 Discussion
The calculated mobility of a-Si TFTs in (3.16) effectively resembles the mobility calcula-
tion for polycrystalline silicon (Psi-TFT) in (3.9) so thatcomparable results can be expected.
However, the Psi-TFT model also includes a variation factorαsat for the onset of saturation
(see (3.11)) in the output characteristicsID vs. VDS. The a-Si RPI model also includes such a
factor, but Necliudov and colleagues did not use it maybe becauseαsat is difficult to separate
from contact effects.
In Table 3.6, a rating of the model for a-Si TFTs according to the model quality chart
defined in Section 3.1 is provided. The accuracy of the model with respect to pentacene tran-
sistors is good as demonstrated in [32]. Modeling of capacitances and bias-induced stress is
not included in the model. The model needs only six technology parameters (RC = RS = RD,
η, VT , µ0, γ, VAA), which increases its compactness (rating good). Contact effects influence
the shape of current-voltage characteristics in a non-linear way. Therefore, parameter extrac-
tion schemes which rely on curve fitting are difficult to employ. This property complicates
parameter extraction (rating bad). Necliudov et al. point out that they use the contact resistors
and diodes mainly to approximate the shape of the output characteristics in the linear region.
However, a more precise procedure would consist of measuring the contact resistances and
barriers beforehand and compensating their effects in the calculations of the other parameters.
Moreover, it was pointed out elsewhere [58] that although a FET with double, opposite diodes
at the electrodes provides a good I/V description, it lacks aphysical basis. Therefore, other
36 Chapter 3. OFET Modeling for Circuit Simulation
research teams use transistor configurations with only two Schottky diodes instead of four in
order to model non-linear contact effects. One diode is placed at the source electrode and the
other at the drain electrode in opposite direction. For example, Brederlow and colleagues [33]
proposed a configuration with a transistor2, two contact resistors and two contact Schottky
diodes, as shown in Fig. 3.7. In normal operation, one diode is forward-biased while the other
operates in reverse breakdown operation. As an additional feature, the barrier height of each
diode is assumed to be gate-voltage-dependent in [33]. Details about theVGS dependence of
the contact diodes can be found in the cited paper. Procedures for dealing with non-linear
contact effects and for extracting diode parameters can be found e.g. in [46, 59].
Source Drain
Gate
Fig. 3.7: Equivalent circuit for contact model with reverse- and forward-biased diodes (adap-tion from [33]).
Table 3.6: MQC for a-Si TFT with contact diodes/resistors.Requirement Rating
Accuracy goodCapacitance Modeling not includedCompactness goodParameter Extraction badStress Effects not included
Necliudov and colleagues [32] analyzed pentacene-based OFETs in bottom-gate config-
uration which were fabricated using lithographic processes. In a recent work by Bartzsch
et al. [60], the a-Si TFT model was successfully applied to all-printed p-type F8T2 transis-
tors. The F8T2 devices could be modeled with ohmic contact resistance (RS = RD = 70 kΩ).
Modeling of contact diodes was not needed for reproducing the measured output characteris-
tics. The reported device parameters are somewhat unexpected. As an example,VAA = 1 GV
andγ = 1 · 10−10 of the investigated device suggest that the gate-source voltage does not
noticeably affect the charge-carrier mobility in (3.16).
2However, the transistor is modeled by a MOSFET model insteadof a TFT model. The approach is focusedon the modeling of the contacts.
3.2. Existing Models for OFETs 37
3.2.4 Analytic VRH Models
In the following, different interpretations of the variable range hopping (VRH) model are
presented. In the VRH approach, thermally activated tunneling of carriers between localized
states, i.e. hopping, is assumed. The first analytical treatment of VRH-driven charge transport
in organic semiconductors was carried out by Vissenberg andMatters [61]. Meijer and co-
workers [62] provided qualitative equations dealing with the VRH-controlled current in the
linear region of OFETs. Calvetti et al. then provided full treatment of output characteristics
of OFETs based on the VRH approach, including calculations of device capacitances [63].
The model treated linear and saturation region and was laterenhanced with equations for
subthreshold current by the same group [64].
In another approach, Fadlallah and colleagues [65] derivedsimilar equations as in [63].
This time, however, the Universal Mobility Law (UML) described by Brown et al. in [3] was
used.
More recent studies by Schliewe and co-workers [66] are alsobased on the VRH approach,
but with emphasis on modeling the effect of the bulk conductivity on the drain current in the
linear region.
3.2.4.1 Meijer Switch-On Model
The switch-on model from Meijer and colleagues [62, 67] approaches transistor behavior
by use of a switch-on voltageVSO instead of the threshold voltageVT . VSO represents the
gate voltage at which accumulation of charge carriers begins (see also discussion on p. 59).
In the switch-on model, the conductivity of the transistor channel is determined using an
adaption of the variable-range hopping model [61]. The adaption employs the percolation-
defined conductivity [67]
σ(δ, T ) = σ0
(
δNt(T0/T )4 sin(π TT0
)
(2α)3BC
)
T0
T
(3.18)
in the gradual-channel approximation. Here,σ0 is a prefactor of the conductivity,δ is a func-
tion of the temperature-dependent charge carrier occupation, Nt is the density of localized
states,T0 is a parameter representing the width of the exponential distribution,α is an effec-
tive overlap parameter between localized states, andBC is a critical number for the onset of
percolation (2.8 in three-dimensional amorphous systems).
38 Chapter 3. OFET Modeling for Circuit Simulation
Meijer and colleagues calculated the drain current from (3.18) according to:
IDS = WL
VDSεsε0σ0
q
(
T2T0−T
)√
2kBT0
εsε0×(
(T0
T )4
sin“
π TT0
”
(2α)3BC
)
T0
T
×[√
εsε0
2kBT0
Ci(VGS−VSO)εsε0
]
2T0
T−1
.
(3.19)
Here,εs andε0 are the relative permittivity of the semiconductor and the free permittivity of
vacuum, respectively.
In the switch-on model, the four parametersσ0, α−1, T0, andVSO are used for modeling
of the output characteristics. Meijer’s results [67] show agreement between experimental
data and simulations of poly(2,5-thienylen vinylene) (PTV), solution-processed pentacene,
and poly(3-hexylthiophene) (P3HT). Typical values for samples of these semiconductors are
given in Table 3.7.
Table 3.7: Representative parameters [67] for solution-processed OFETs modeled by the Mei-jer switch-on model.
Material T0 [K] σ0 [106 S/m] α−1 [Å] VSO [V]
PTV 382 5.6 1.5 1Pentacene 385 3.5 3.1 1P3HT 425 1.6 1.6 2.5
3.2.4.2 Brescia VRH model
While Meijer and co-workers used their VRH equations only asa tool to study the physical
properties of different materials, Calvetti and colleagues [63] from the University of Brescia,
Italy, elaborated an analytical model useful for circuit simulators like SPICE. The drain current
reads
ID = βW
L
T
2T0
[
(VGS − VSO)2T0/T − (VGS − VDS − VSO)2T0/T]
(3.20)
for an n-type device in the linear region (VGS − VSO > VDS) and
ID = βW
L
T
2T0(VGS − VSO)2T0/T (3.21)
in the saturation region forVGS − VSO ≤ VDS. The reader should note that in the original
publication [63], the flat-band voltageVFB is used for denoting the onset of accumulation. For
consistency reasons, however,VSO will be used in the following. The parameterβ is defined
3.2. Existing Models for OFETs 39
as
β =σ0
q
T
2T0 − T
C2T0/T−1is
(2kBT0εsε0)T0/T−1
(
(T0/T )4 sin(πT/T0)
(2α)3BC
)T0/T
. (3.22)
In this equation, the parameters have their meaning as defined in Section 3.2.4.1. Calvetti et al.
also used the parameters in Table 3.7 and assumedεs = 3.0 as well asCis = 1.3 × 10−4 F/m2.
The Brescia model also treats the calculation of dynamic model behavior by specifying
equations for the induced chargesQS , QD, andQG at the terminals source, drain, and gate.
The calculations give rise to somewhat lengthy expressions. As an example,QG reads
QG = −WLCisQGnum
QGden, (3.23)
QGnum =T
2T0 + T(V
2T0
T+1
GST − V2T0
T+1
GDT ) +kBT
q(V
2T0
T
GST − V2T0
T
GST ), (3.24)
QGden =T
2T0
(V2T0
T
GST − V2T0
T
GDT ) +2T
2T0 − T
kBT0
q(V
2T0
T−1
GST − V2T0
T−1
GDT ). (3.25)
Here,VGST = VG − VS − VSO, andVGDT = VG − VD − VSO. FromQG, the gate-source
and gate-drain capacitances can be derived using
CGS =QG
VGS
∣
∣
∣
∣
VGD=const, CGD =
QG
VGD
∣
∣
∣
∣
VGS=const. (3.26)
Fig. 3.8 shows a comparison of calculated capacitancesCGS andCGD in the Brescia VRH
model with capacitances calculated by the Meyer model used in MOSFET models, both nor-
malized toCg = WLCis. Gate charge in the Meyer MOSFET model was calculated using
QG =2
3Cis
V 3GST − V 3
GDT
V 2GST − V 2
GDT
. (3.27)
The plots were calculated for an OFET with pentacene as active layer. As indicated by the
plots, conventional Meyer model predicts capacitances with slightly different values than com-
puted with the Brescia capacitance model. The reader shouldnote, however, that these calcu-
lations do not include the contribution of the overlap capacitance of the source/drain fingers
(see Fig. 2.4). If e.g. the drain/source fingers are assumed to have the same widths as the
length of the channel, additional overlap capacitancesCGSO = CGDO = Cg/2 would have
to be included. Consequently, the curves in Fig. 3.8 would have to be shifted up by 0.5. A
comparison of the curves shows that Meyer-based modeling ofcapacitances already provides
reasonable first-order approximation. Meyer-modeling ofCGS will lead to voltage-dependent
capacitances (without considering overlap capacitances)which are 2% to 12% below the val-
ues predicted by the Brescia model. ForCGD, the Brescia-modeled values can lag behind the
40 Chapter 3. OFET Modeling for Circuit Simulation
Meyer-modeled capacitance values by up to 40%.
MeyerVRH Meyer
VRH
0.55
0.6
0.65
0.7
−30 −25 −20 −15 −10 −5 0
0.1
0.2
0.3
0.4
−30 −25 −20 −15 −10 −5
CG
S/C
g
VGS [V]
CG
D/C
g
VGS [V]
Fig. 3.8: Comparison of capacitance ratiosCGS/Cg andCGD/Cg calculated with the Brescia(solid lines) and Meyer model (stars), respectively.T0 = 385 K (for pentacene) was used inthe VRH calculations.
Calvetti and colleagues also derived equations for the subthreshold region [64]. These
equations were found by numerical simulations of the two-dimensional potential and charge
distribution within the channel in the subthreshold region. The simulations showed that in
the subthreshold region, the conductivity is modulated by the depletion of the carriers in the
semiconductor layer. Moreover, the drain current in subthreshold operation can be determined
using the gradual channel approximation. However, the resulting relations are quite compli-
cated and will not be reproduced here. They can be found in [64].
3.2.4.3 UML Model
The model from Fadlallah and co-workers [65] is based on the observation by Brown and
colleagues [3] that the conductivityσ of charge carriers in a semiconductor film is given by
an empirical equation
σ = K ′NγA, (3.28)
whereNA is the doping-induced charge density in the semiconductor,K ′ andγ are fitting
parameters. The charge-carrier mobilityµ is then approximated by the simple power law
µ = KNγ−1A . (3.29)
3.2. Existing Models for OFETs 41
Here,K is another fitting parameter. Brown et al. showed that this empirical power law can
be applied to a variety of polymer materials. Hence, the law is referred to as theUniversal
Mobility Law (UML) in [65]. (3.29) can be employed for the mobility in the gradual channel
approximation in order to get
ID,lin =K
(2m + 1)(2m + 2)
W
L
C2m+1is
(2kBTε0εs)m
[
V2(m+1)GST − (VGST − VDS)2(m+1)
]
(3.30)
for the linear region (VGS − VT > VDS) of a p-type OFET. Here,m = γ − 1 and the voltage
VGST = VGS − VT while the other parameters have their usual meaning. The drain current in
the saturation region (VGS − VT < VDS) is given as
ID,sat =K
(2m + 1)(2m + 2)
W
L
C2m+1is
(2kBTε0εs)m(VGS − VT )2m+2[1 + λ(VDS − VGST ]. (3.31)
The cut-off current (forVGS > VT ) is assumed to be independent of both the drain-source
voltage and the gate-source voltage and is modeled by
ID,off = I00W. (3.32)
I00 is the current density in the cut-off region andW is the channel width of the device.
Modeling of capacitances on the basis of the UML model is alsopresented in [65]. The
threshold voltageVT was assumed to be equivalent to the switch-on voltageVSO of the device
so to get the total charge on the gate electrode of
QG = CisWL(2m + 2)
(2m + 3)· V 2m+3
GDT − V 2m+3GST
V 2m+2GDT − V 2m+2
GST
. (3.33)
Here,VGDT = VG − VD − VSO, VGST = VG − VS − VSO. It should be noted that ensuring
VGST ≥ 0 andVGDT ≥ 0 is necessary in the calculations in order to yield a correct charge in
(3.33). The gate-source capacitance is
CGS =∂QG
∂VGS
∣
∣
∣
∣
VGD=const
= −Cis · W · L · V 2m+1GST · 2m + 2
2m + 3
×
(2m + 2)V 2m+3GDT − (2m + 3)V 2m+2
GDT VGST + V 2m+3GST
(V 2m+2GDT − V 2m+2
GST )2
. (3.34)
42 Chapter 3. OFET Modeling for Circuit Simulation
Similarly, the gate-drain capacitance is equivalent to
CGD =∂QG
∂VGD
∣
∣
∣
∣
VGS=const
= −Cis · W · L · V 2m+1GDT · 2m + 2
2m + 3
×
(2m + 2)V 2m+3GST − (2m + 3)V 2m+2
GST VGDT + V 2m+3GDT
(V 2m+2GDT − V 2m+2
GST )2
. (3.35)
Fadlallah and colleagues carried out validations of the Eldo implementation in order to
test the convergence in transient simulations of a ring oscillator. The ring oscillator consisted
of inverters in diode configuration (load transistor with gate and drain at negative supply, both
transistors with PTAA as semiconducting material). A comparison between measured and
simulated oscillation signals was not given in the publication.
The UML model and the Brescia model are almost identical if the following parameter
translation is used:
K =σ0
q
((
T0
T
)4sin(π T
T0)
(2α)3BC
)
T0
T
, m =T0
T− 1. (3.36)
The UML model provides treatment of the channel-length modulation while the Brescia
model contains more sophisticated equations dealing with the subthreshold currents. More-
over, the Brescia model works with the term2kBT0εsε0 while the UML model resorts to
2kBTεsε0.
3.2.4.4 Hamburg VRH Model
In another approach, Schliewe and colleagues [66] derived VRH equations for the steady-state
drain current:
ID = −W
L
aCis
b + 2
[
rb+2(VSO − VGS) − rb+2(VSO − VGD)]
. (3.37)
Here,a andb are parameters derived from the relationship between the mobility and the gate
voltage
µ(x) = a(VSO − VGx)b. (3.38)
VGx represents the voltage between the gate and the positionx along the semiconductor-
insulator interface,VSO is the switch-on voltage.r is a step function which allows using one
3.2. Existing Models for OFETs 43
unified equation for the linear and saturation region. It is defined as
r(V ) =
V, V ≥ 0
0, V < 0.(3.39)
(3.37) and (3.30) are equivalent for
a =K
2m + 1
C2mis
(2kBTε0εs)m, b = 2m. (3.40)
3.2.4.5 Discussion
The analytical VRH models presented in this section are physics-based models which qualita-
tively predict transistor behavior. In this way, they differ from other models discussed earlier
in this chapter. The other models simply extend existing approaches developed for inorganic
technologies.
Table 3.8 provides a rating of the physical models with respect to the model quality chart
presented in Section 3.1. Accuracy has been rated as good according to the data provided in
[62, 63, 65, 66, 67]. Modeling of capacitances is included. The physical models work with a
limited set of parameters, which improves their compactness and leads to a rating of good in
this category. Parameter extraction has been rated as medium because it is more difficult than
in the case of Level-1 modeling. Stress effects are not included in any of the analytical VRH
models.
Table 3.8: MQC for analytical VRH models.Requirement Rating
Accuracy goodCapacitance Modeling goodCompactness goodParameter Extraction mediumStress Effects not included
3.2.5 General Table-based Models
Table-based models avoid the problems of parameter extraction. These models store tables
of output characteristics in a compressed form. The tables are then used in the simulations in
order to derive the behavior of a device. Such approaches completely disregard physics-based
parameters and instead focus on accurate reproduction of measured values.
44 Chapter 3. OFET Modeling for Circuit Simulation
In Table 3.9, table-based models have been rated according to the model quality chart
developed in Section 3.1. Accuracy in reproducing a reference device is excellent because
its characteristics are stored in a table. Modeling of capacitances can also be carried out
accurately by use of tables if the simulation environment supports tables for nodal charges
(e.g. Tanner T-Spice [68]). Parameter extraction is not required.
Compactness has been rated as bad because table-based modeling generally does not pro-
vide parameters which can be accessed by the users. Moreover, these internal parameters
are without physical meaning or relations to device structure. This fact complicates those
statistical modeling approaches where correlations between variations of physical and/or ge-
ometrical device properties and output characteristics are analyzed. Therefore, stress effects
are also difficult to include in the models.
Owing to the missing influence on the output characteristics, table-based modeling is not
suited for the exploratory study of parameter variations. However, it can be a viable tool in
combination with two-dimensional transistor simulators because it provides rapid modeling
without the need to derive model parameters.
Table 3.9: MQC for table models.Requirement Rating
Accuracy goodCapacitance Modeling goodCompactness badParameter Extraction not neededStress Effects not included
3.2.6 Dresden Model
Gay and colleagues [69] from the Dresden University of Technology developed a model which
completely disregards the physical background of modeling. Instead, it resorts to powerful
fitting functions and focuses on the simulation of analog circuits which require accurate tran-
sistor models [25].
3.2.6.1 Model Equations
The Dresden model is based on the observation that the individual curves of the output charac-
teristicsID vs. VDS are similar in shape. A curve for a particular gate voltageVGS,0 is used as
a template and is described by a reference or shape functionf and powerful fitting functions
3.2. Existing Models for OFETs 45
that mapf to alternate geometries andVGS values. The drain current is described as
ID = KG · f[
VDS
τ(VGS)
]
· h(VGS). (3.41)
Here,KG is a geometry factor which scales arbitrary transistors to the geometry of a reference
transistor for which the functionf is derived.KG is calculated according to
KG =W/L
WR/LR
, (3.42)
whereW/L andWR/LR are the width-to-length ratios of the actual and the reference de-
vice, respectively.f approximates the current-voltage shape of the reference transistor at a
predefined gate voltageVGS,0. It is defined as
f(VDS) = −10Xf with Xf =∑
i
ai exp(−biVDS). (3.43)
Here,ai andbi are fitting parameters used for approximating the referencecurve. The scale
functionh scales the drain current with respect to differentVGS values whereh(VGS,0) = 1.
The approximation function is
h(VGS) = 10Xh with Xh =∑
i
ci · exp(−di · VGS). (3.44)
Here,ci anddi are fitting parameters. The delay functionτ is used for stretching the reference
functionf with respect to differentVGS values whereτ(VGS,0) = 1. τ is defined as
τ(VGS) = 10Xτ with Xτ =∑
i
pi · exp(−qi · VGS). (3.45)
Again,pi andqi are fitting parameters.
The parametersai andbi in the reference functionf are fitted to measured drain current
points.ci, di andpi, qi are then concurrently extracted with an optimization scheme.
Device variability is introduced by additional parametersin the drain current equations:
ID = Ks · KG · f(
VDS
τ + τs
)
· h(VGS − VON). (3.46)
Here,KS is a current scale factor,VON is used for shifting the switch-on voltage, andτs is
used for shifting the delay of the transition between the linear and the saturation region. Gay
and colleagues modeled these three parameters with normal distributions, which they obtained
from measurements.
46 Chapter 3. OFET Modeling for Circuit Simulation
Fig. 3.9 shows the output characteristics and the fitting functions for a pentacene device
generated with parameters from Table 3.10.
3.2.6.2 Discussion
In the Dresden model, the functionf from (3.43) is used for compressing the measured values
into a more tractable form. Gay et al. use power series in order to approximate the shape of
measured drain current values. They thereby ignore any physical background responsible for
the shape of the curves.
The numerous parameters in the model can be derived easily but are not based on any
physical assumption or meaning. Therefore, there is no direct relationship to material or
process properties.
The Dresden model accounts for dynamic hysteresis effects by adding an RC network
which simulates the delayed transport of mobile charges within the insulator [69]. Moreover,
statistical variation of individual devices is addressed.
Table 3.11 contains ratings for the Dresden models according to the model quality chart
presented in Section 3.1. Accuracy has been rated as good according to the comparisons be-
tween the model and measurement data presented in [69]. The compactness has been rated
as bad because many fitting coefficients (14 in the example from Table 3.10) without physical
meaning are needed. In the parameter extraction, curve fitting is necessary. The fitted param-
eters are not independent of each other because there is no “true” set of parameters describing
the transistor. When differentVGS0 values are used (i.e. different shape functionsf ), differ-
ent coefficients result. Therefore, the parameter extraction has been rated as medium. Stress
effects are included in the model by simple RC networks. Hence a rating of medium has been
given. Explicit modeling of capacitances is not mentioned in [69]. Judging from results pre-
sented in [69], constant capacitors forCGS andCGD are probably used. The Dresden model
easily copes with contact effects. Nevertheless, there is no link between the fitting coefficients
and physical or structural parameters. As an example, the influence of contact resistances is
hidden in the fitting coefficients from which it cannot readily be extracted. Moreover, phys-
ically meaningful parameters like the threshold voltage are missing. Therefore, the Dresden
model is of limited use for device technologists who want to explore the influence of future
process changes on electrical device parameters.
3.2.7 Modeling of Complementary OFETs
The modeling of transistors used in complementary organic circuits is no special problem as
dedicated models for the n-type and p-type transistors can be used.
3.2. Existing Models for OFETs 47
Table 3.10: Fitting parameters for typical bottom-gate bottom-contact pentacene transistor[69] with pronounced contact resistance.
Shape functionf Scale functionh Delay functionτa1 -1.2737 b1 0.4115 c1 -3.8416 d1 0.2432 p1 -1.9399 q1 0.1215a2 -6.7432 b2 1.2e-4 c2 0.8047 d2 -0.0175 p2 1.1035 q2 0.0277a3 -1.0077 b3 1.9633 – – – – – – – –
0.5
1.5
2.5
3.5
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8 4.0
3.0
2.0
1.0
0.0
1.0
−4.0
−6.0
−8.0
0.0
−10u
−20u
−30u
−40u
−50u
−60u
−70u
0u
−14 −12 −10 −8 −6 −4 −2 0
−10 −8 −6 −4 −2 −10 −8 −6 −4 −2 0 0
−2.0
−10.0
−12.0
−14.0
−16.0
−18.0
−14 −12 −10 −8 −6 −4 −2 0
I D[A
]h(V
GS)
f(V
GS)
τ(V
GS)
VDS [V]
VGS [V] VGS [V]
x 10−8
x
Fig. 3.9: Transfer characteristic and Dresden-type fittingfunctions for a sample pentacenetransistor ([69]).
48 Chapter 3. OFET Modeling for Circuit Simulation
Table 3.11: MQC for Dresden model.Requirement Rating
Accuracy goodCapacitance Modeling not includedCompactness badParameter Extraction mediumStress Effects medium
3.2.8 Modeling of Ambipolar OFETs
OFETs normally operate as unipolar devices where only one type of carriers (holes in p-type
and electrons in n-type semiconductors) contributes to thecurrent flow. Ambipolar devices
are a special class of OFETs where both holes and electrons can contribute to the current
flow, depending on the bias voltages at drain, gate, and source. The operation of ambipolar
devices will be explained in the following with the aid of [13, 58]. Here, a zero threshold
voltage and positive drain and gate voltages will be assumed. When the gate voltage lies in
the range between the drain and source voltage, the drain side of a standard unipolar transistor
normally gets pinched off. In ambipolar devices instead, charge carriers of opposite polarity
are accumulated in this region. The device is then effectively composed of two regions in
series as shown in Fig. 3.10: a hole-accumulating region of lengthLp is series-connected to
an electron-accumulating region of lengthLn.
With the assumption of equal currents in both regions, i.e.
1
2
W
LpCisµp(VDS − VGS)2 =
1
2
W
LnCisµnV
2GS, (3.47)
and a total length
Ln + Lp = L, (3.48)
the drain current forVDS > 0 is
ID =1
2
W
LCis[µnV
2GS + µp(VDS − VGS)2]. (3.49)
(3.49) is equivalent to a p-type and an n-type transistor of equal dimensionsW andL in
parallel. For the p-type device, however, the position of the drain and source electrodes is
flipped owing to the requirement thatVS,p > VD,p, whereVS,p and VD,p are the effective
source and drain voltages of the p-type device. During aVDS sweep with a fixedVGS, the
n-type device is operated in normal FET mode while the p-typedevice has a constant gate-
drain voltageVGD,p. Hence, the latter displays a diode-like drain current, which increases
3.2. Existing Models for OFETs 49
holes
electrons
char
ge d
ensi
ty
0position along the channel
pote
ntia
l
drain source
Lp Ln
VDS
VGS
Fig. 3.10: Schematic charge and potential distribution in the channel of an ambipolar OFETwith VS < VG < VD (adaption from [58]).
with decreasing gate voltages. Therefore, a diode-like characteristic adds to the normal drain
current, which also increases with reduced gate-source voltage.
For VDS < 0, the situation is reversed and the p-type device acts as the normal transistor
and the n-type device contributes current in diode-like form.
Fig. 3.11 shows the schematic output characteristics of an ambipolar OFET. For the I/V
curves, a p-type transistor and an n-type transistor in parallel with µn = µp = 10−4 cm2/Vs
have been assumed. In order to show the individual contributions of the two transistors,
VT,n = 10 V andVT,p = -8 V have been chosen.
Models developed in literature on ambipolar OFETs can be reduced to a parallel combina-
tion of a p-type and an n-type transistor. Schmechel et al. [70] used simple Level-1 equations
(see Section 3.2.1) to map drain-current behavior. Meijer and co-workers [13] employed an
analytic VRH model (see Section 3.2.4) in order to explain the increasing influence of the
gate-source voltage. Both models can be implemented using aparallel combination of the re-
spective unipolar devices, i.e. p-type and n-type Level-1-modeled devices for the Schmechel
approach as well as p-type and n-type VRH-modeled devices for the Meijer approach.
50 Chapter 3. OFET Modeling for Circuit Simulation
4.0u
3.0u
2.0u
1.0u
0.0u
−1.0u
−2.0u
−3.0u
−4.0u
−30 −20 −10 0 10 20 30
VGS= 20 V0 V
-20 V
0 V
5 V
15 V 10 V
VDS [V] →
I D[A
]→
Fig. 3.11: Schematic output characteristic for an ambipolar OFET with gate-source voltageswept from -20 to 20 V.
3.3 Popular Procedures for Parameter Extraction
Users of transistor models are interested in simple extraction procedures for relevant model
parameters like threshold voltage or mobility. Numerous approaches can be used for extract-
ing important parameters. In the following, frequently used procedures will be presented. A
more thorough analysis of suitable extraction procedures for the threshold voltage and other
important device parameters can be found e.g. in [27, 71, 72,73, 74, 75].
3.3.1 Procedures for the Level-1 Model
In this section, popular extraction methods for parametersof the Level-1 model are listed.
These methods are also frequently used in the extraction of OFET parameters.
Threshold Voltage
The threshold voltageVT is one of the three parameters of the Level-1 model.VT can be ex-
tracted in numerous ways. In the following, some frequentlycited methods will be presented.
3.3. Popular Procedures for Parameter Extraction 51
1. Extraction in the Linear Region
VT can be extracted by plotting the channel conductance
gd =∂ID
∂VDS≈ β(VGS − VT ) (3.50)
for “small values” ofVDS [76]. In literature on parameter extraction, voltages in the order of
10 mV are proposed forVDS [71]. Fig. 3.12 illustrates a simulated sample curve3 for (3.50).
0.0 0 10 20 30 40 50
1.0u
2.0u
3.0u
4.0u
5.0u
6.0u
0.0
10.0u20.0u30.0u40.0u
50.0u60.0u
70.0u80.0u
90.0u
0 10 20 30 40 50
slopeβ · VDS
VTI D[A
]
VGS [V]
VTslopeβ
g d[A
/V]
VGS [V]
Fig. 3.12: Plot of channel conductancegd vs. VGS and drain currentID vs. VGS. Both plotsare forVDS = 10 mV. Data has been taken from a simulated device which operates accordingto the Level-1 equations.
Extrapolating the channel conductance curve to zero leads to the threshold voltage asgd =
0 A/V at VGS equal toVT in (3.50).
The drain currentID can also be used for extracting the threshold voltageVT without
the need to derivegd (also shown in Fig. 3.12). Again,VT is obtained by inspecting the
extrapolated intersection ofID with theVGS axis at zero current. The extrapolation is done
at the point of maximum slope, i.e. where the transconductancegm = ∂ID/∂VGS reaches its
maximum [71].
By extrapolatinggd or ID in the linear region, series resistance at source and drain of the
device can be neglected as a drain-source voltageVDS ≪ 1V is used. On the other hand, the
transfer characteristic of real OFET devices can considerably deviate from the idealistic Level-
1 model. This generally complicates finding the most useful extrapolation point required in
the intercept calculations.
3Model data: n-type device,KP = 1 nA/V2, VT = 8 V, λ = 1 · 10−3 1/V, W/L = 200.
52 Chapter 3. OFET Modeling for Circuit Simulation
2. Extraction in the Saturation Region
In the saturation region,VT can be extracted by inspecting the transconductancegm. The
transconductance of a transistor denotes the variation of the output current resulting from a
variation of the input voltage and is calculated in the saturation region by
gm =∂ID
∂VGS
∣
∣
∣
∣
VDS=const= β(VGS − VT ). (3.51)
In (3.51), the channel-length modulation is neglected by setting λ = 0. Extrapolation of the
transconductance curve to zero leads to the threshold voltageVT [76].
Alternatively, the square root of the drain current can be used. From (3.3)
√
ID =
√
β
2(VGS − VT ), (3.52)
results when again neglecting the channel-length modulation. The threshold voltageVT is
extracted by extrapolating√
ID to zero [77]. Fig. 3.13 depicts the extraction procedure forthe
gm and√
ID method.
0.0
10.0u
20.0u
30.0u
40.0u
50.0u
60.0u
70.0u
80.0u
0 10 20 30 40 500.0
5.0m
10.0m
15.0m
20.0m
25.0m
30.0m
35.0m
40.0m
0 10 20 30 40 50
VT slopeβ
VGS [V]
g m[A
/V]
VT slope√
β2
VGS [V]
√I D
[√A
]
Fig. 3.13: Plot of the transconductancegm vs. VGS and the square root of the transfer charac-teristic. Data have been taken from a simulated device with Level-1 equations.
Mobility
With the threshold voltage established, other parameters like the charge-carrier mobilityµ can
be analyzed.µ is an important parameter in the assessment of device performance and is often
used as a benchmark number (see e.g. [78]) in the comparison of different semiconductors.
In this section, extraction methods for the mobility are presented.
3.3. Popular Procedures for Parameter Extraction 53
1. Extraction in the Linear Region
From the slope ofgd or ID in Fig. 3.12, the device conductance parameterβ can be established
[77]. According to (3.5),
µ =β
Cis
L
W. (3.53)
It can also be calculated at individual points using the transconductance parameter
gm ≈ βVDS (3.54)
in the linear region. Solving this equation with respect toβ and inserting (3.53) [79] leads to
µ =L
W
gm
CisVDS. (3.55)
2. Extraction in the Saturation Region
In the saturation region, the slopes of thegm and√
ID curves as shown in Fig. 3.13 can be
used for deriving the device conductance parameterβ. (3.53) can then be employed in the
extraction of the mobilityµ.
Alternatively, the mobility can be calculated at individual points. By inspecting the transcon-
ductancegm from (3.51), the mobility can be calculated using (3.53) [80] with
µ = gm · L
W
1
Cis(VGS − VT ). (3.56)
In [78], the mobility is calculated by deriving (3.52) with respect to the gate-source voltage
∂√
ID
∂VGS=
√
W
2LµCis (3.57)
and solving for the mobility
µ = 2CisL
W
(
∂√
ID
∂VGS
)2
. (3.58)
In order to solve (3.56)VT has to be available while (3.58) and (3.55) are independent of
VT . Nevertheless, calculation of the derivatives is needed.
Channel length Modulation
The channel length modulation parameterλ can be extracted from the saturation region of the
output characteristics when the threshold voltage and the device conductanceβ are known.
54 Chapter 3. OFET Modeling for Circuit Simulation
The saturation current is given as
IDSat = β(VGS − VT )2(1 + λVDS). (3.59)
This relationship gives rise to two approaches. First, the channel conductance including
the channel length modulation
gd =∂ID
∂VDS
= λβ(VGS − VT )2 (3.60)
can be used for calculating the channel-length modulation.This results in a value of
λ =
∂ID
∂VDS
β(VGS − VT )2. (3.61)
It can also be derived graphically by inspecting the slope ofthe channel conductance in the
saturation region with respect to the drain-source voltageVDS as shown in Fig. 3.14.
0.0
5.0u
10.0u
15.0u
20.0u
25.0u
30.0u
35.0u
40.0u
45.0u
0 10 30 40 50 20VDS [V]
≈ 490 nA/V
g d[A
/V]
Fig. 3.14: Extrapolation ofλ from the channel conductance (gd) vs. drain-source voltageVDS
plot.
Contact Resistance
The Level-1 model does not include the influence of contact resistances between the transistor
channel and the source and drain electrodes. Nevertheless,the role of contact resistances in
transistor modeling is very important as will be shown in thefollowing. Contact resistances
3.3. Popular Procedures for Parameter Extraction 55
can be modeled by adding series resistors to the transistor as shown in Fig. 3.15.
GM VDS
D
DP
SP
RS
RD
VGS
S
Fig. 3.15: Elementary Level-1 transistor with contact resistors at drain and source.
The schematic in Fig. 3.15 contains a transistorM . The device has two series resistors
RS andRD which account for the contact resistance at the source and drain electrodes to the
channel. Both resistors affect the transistor voltages in away such that the actual gate-source
voltageV ′
GS between nodesG andSP is
V ′
GS = VGS − ID · RS (3.62)
and the actual drain-source voltageV ′
DS between nodesDP andSP is
V ′
DS = VDS − ID · (RS + RD). (3.63)
In the following, the influence of the series resistors will be analyzed. First,RD shall be
neglected (RD = 0 Ω) and for simplified calculations,λ shall be dropped (λ = 0), too. The
drain current in the saturation region can then be expressedby inserting (3.62) and (3.5) into
(3.3):
ID =β
2(V ′
GS − VT )2 =β
2(VGS − ID · RS − VT )2. (3.64)
The solution for this equation is given by [81]
ID =1 + 2βRSVGST −
√1 + 4βRSVGST
2βR2S
, (3.65)
with VGST = VGS − VT . The source resistanceRS reduces the effective device conductance
56 Chapter 3. OFET Modeling for Circuit Simulation
parameterβ. Fig. 3.16 illustrates this behavior.
40 V
20 V
30 V
0.0
1.0m
1.2m
1.4m
1.6m
1.8m
2.0m
0 10 20 30 40 50
0.8m
0.6m
0.4m
0.2m
VGS = 50 V
VDS [V]
I D[A
]
Fig. 3.16: Effect of the source resistance on the drain current: simulated curves for a transistorwith RS (dashed lines) and the same transistor without the contact resistance (solid lines).
If only RD is considered (RS = 0 Ω), the drain current in the saturation region does not
change but the boundary between the linear and saturation region shifts as demonstrated by
the following equation (VSat = effective saturation voltage,V ′
Sat = saturation voltage between
DP andSP ):
VSat = V ′
Sat + β · V 2GST · RD
VGST =V ′
Sat= VGST + βV 2GST · RD. (3.66)
An effective threshold voltageV ∗
T can be derived from (3.66) by noting that
V ∗
T = VT − βRDV 2GST . (3.67)
(3.67) shows that the effective threshold voltageV ∗
T depends onVGST by a square-law
relationship forRS = 0 Ω. Its influence on the drain current is shown in Fig. 3.17.
If both series resistors are active (RS > 0 Ω andRD > 0 Ω) andV ′
GST = V ′
GS − VT then
VSat = V ′
Sat + IDSat · (RS + RD) = V ′
GST + β(RS + RD)V ′2GST . (3.68)
The above discussion shows that the contact resistance degrades device performance by
reducing the effective drain-source and gate-source voltages. There exist various methods of
determining the contact resistance. In the following, three frequently used methods will be
3.3. Popular Procedures for Parameter Extraction 57
40 V
30 V
20 V
0.0
0.6m
1.0m
1.2m
1.4m
1.6m
1.8m
2.0m
0 10 20 30 40 50
0.8m
0.4m
0.2m
VGS = 50 V
VDS [V]
I D[A
]
Fig. 3.17: Effect of drain resistance on the drain current: simulated curves for a transistor withRD (dashed lines) and the same transistor without the contact resistance (solid lines).
presented.
1. Determination by Channel Length Variation
Using a systematic variation of the channel length, the resistance between source and drain
can be measured in the linear region as
RM =VDS
ID
=L
W
1
µCis(VGS − VT )+ Rc = G0 · L + Rc. (3.69)
Here, Rc is the contact resistance (RC = RS + RD) while G0 is the contribution of the
transistor independent of its channel length. The latter isdefined as
G0 =1
W · µCis(VGS − VT ). (3.70)
The contact resistance can then be established by measuringthe drain-current characteris-
tics for transistor devices with identical transistor widths but varying lengths and extrapolating
Rc from theRM vs. L plot toL = 0 µm. Fig. 3.18 shows a sample curve for the approach.
2. Determination with Potential Profiling
This method is directly applicable to transistors with a bottom-gate bottom-contact structure
where the semiconductor is deposited last and the potentialprofile along the channel can be
58 Chapter 3. OFET Modeling for Circuit Simulation
30 V
40 V
50 V
0.0
1.0M
1.5M
2.0M
200.0u150.0u100.0u50.0u0.0
0.5MRC
VGS = 20 VVDS = 1 V
L [m]
RM
[Ω]
Fig. 3.18: Measured resistance (RM ) vs. channel length (L) of devices with fixed channelwidth: squares are the values according to (3.69) and solid lines are obtained from SPICEsimulations atVDS = 1 V.
measured by use of potential probes ([44, 82]). Alternatively, sampling electrodes similar
to four-point probes [83] have to be present in the channel inorder to measure the channel
potential at predefined locations. A sample profile for a device operating in the linear region
is depicted in Fig. 3.19. On they axis, the potential profile is plotted withx being the position
along the channel. At the source contact,x = 0 µm and at the drain contact,x = L. L is the
length of the transistor channel. The valueRS for the source contact resistance and the value
RD for the drain contact resistances can be readily extracted from the potential drop at source
and drain.
3. Determination with the SJ method
The idea of the SJ method (named after its inventors Suciu andJohnston [84]) is to assume
thatID can be modeled in the linear region by
ID = β(VGS − VT )V ′
DS = β(VGS − VT )(VDS − ID · RC), (3.71)
with V ′
DS being the actual drain-source voltage at the transistor andRC the sum of source and
drain resistance (RS + RD). The explicit form of (3.71) is
ID =β(VGS − VT )
1 + RCβ(VGS − VT )VDS. (3.72)
3.3. Popular Procedures for Parameter Extraction 59
position0 L
source drain
elec
tric
pot
entia
ly
x
RS · ID
RD · ID
Fig. 3.19: Schematic potential profile along the channel of abottom-gate bottom-contact tran-sistor (adaption from [82]).
(3.72) can be rearranged to yield
x
ID/VDS=
1 + RCβ · xβ
≡ E(x) = E0 + ∆Ex, (3.73)
wherex = VGS−VT andID/VDS is the reciprocal of the resistanceRM which can be measured
by takingID from a real device. (3.73) is equivalent to
x · RM = E0 + ∆Ex, (3.74)
with E0 = 1/β and∆E = RC . Fig. 3.20 illustrates the resulting curveE(x).
Suciu and Johnston emphasize that their approach is an analytical extraction procedure
which does not need any optimization procedures. Although the influence of the source re-
sistanceRS on the gate-source voltageVGS is neglected in the calculations, the error can be
minimized by taking the measurements at smallID values.
3.3.2 Extraction Procedures for TFT Models
The most important parameter in the model for Psi-TFTs is thethreshold voltage from which
the other parameters depend in an extraction procedure. Jacunski et al. [47] give two practical
definitions of the threshold voltage:
1. The voltage above which the drain current no longer exponentially depends onVGS.
2. The voltage above which a MOS-like drain current expression can be used.
60 Chapter 3. OFET Modeling for Circuit Simulation
0.0
2.0M
4.0M
6.0M
8.0M
10.0M
12.0M
14.0M
50.0 40.0 30.0 20.0 10.0 0.0
VDS = 1 V
∆E = RC
E0 = 1β
VGS [V]
E(x
)
Fig. 3.20: Plot of the extraction functionE(x) for the contact resistance.
Threshold voltages obtained by the first definition can considerably differ from voltages de-
rived with the other solution as there is a broad transition range from subthreshold operation in
the first definition to accumulation operation from the second definition. The second method
was also adopted by the IEEE standard on the characterization of OFET devices [48]. This
standard defines the threshold voltage as the minimum gate voltage required to induce the
channel. The value is extracted fromIDS vs. VGS measurements.
The definitions in [47] demonstrate the difficulties in exactly describing the threshold volt-
age. In the case of conventional silicon MOSFETs, the threshold voltage is defined as the
gate-source voltage where the strong inversion layer starts to form. For inorganic thin-film
transistors, an additional on-voltageVON was introduced [41].VON is found by inspecting
the logID vs. VGS curve at low drain-source voltages. The on voltage is the point where
log ID reaches its minimum and becomes linear. According to [41], the physical meaning of
VON in polycrystalline silicon TFTs is that atVGS = VON the transistor channel starts form-
ing. However, induced carriers are still trapped in band-gap states. At a gate bias equal to
the threshold voltageVT , induced charges begin to appear as mobile carriers in the channel.
Fig. 3.21 illustrates the differences betweenVON andVT .
[62, 85] simply defineVON as the switch-on voltage. This voltage is the value ofVGS
where the lowest drain current is measured. A similar definition is used in the RPI model.
In the grain-boundary model, the mobilityµ depends on the gate-source voltage (see (3.8)
and (3.9)). Therefore, obtaining the threshold voltageVT by plotting√
ID vs. VGS as usually
applied in literature on parameter extraction leads to incorrect values. Extracted threshold
voltages tend to be more favorable than the true parameter. Fig. 3.22 illustrates this behavior.
3.3. Popular Procedures for Parameter Extraction 61
100.0f
1.0p
10.0p
100.0p
1.0n
10.0n
100.0n
1.0u
10.0u
100.0u
−4 −2 0 2 4 6 8 100.0
5.0m
10.0m
15.0m
20.0m
25.0m
30.0m
35.0m
VTVON
I D[A
]
VGS [V]
3√I D
[3√
A]
Fig. 3.21: Definition ofVON andVT .
The plot shows logID and√
ID of a simulated transistor. In the simulation,ID ∼ (VGS−VT )3
in saturation andVT = 1 V was used. The parameter set of the device is identical to theone
used in Fig. 3.21. An extraction with square-root plotting leads to the incorrect threshold
voltage ofVT ≈ 3 V.
100.0f
1.0p
10.0p
100.0p
1.0n
10.0n
100.0n
1.0u
10.0u
100.0u
−4 −2 0 2 4 6 8 100.0
1.0m
2.0m
3.0m
4.0m
5.0m
6.0m
7.0m
VT
VGS [V]
I D[A
]
√I D
[√A
]
Fig. 3.22: Extraction of the threshold voltage by use of the√
ID vs. VGS method on a transistorwith ID ∼ (VGS − VT )3 in the saturation region.
62 Chapter 3. OFET Modeling for Circuit Simulation
The preceding discussion shows that knowing the power factor α in the current expression
ID ∼ (VGS − VT )α for the saturation current is necessary in order to correctly extract the
threshold voltageVT .
The power factorα can e.g. be derived by plotting logID vs. log(VGS − VT ). The slope
of the resulting line yieldsα. In Psi-TFT modeling,α = mµ +2 and should not be intermixed
with αsat. Heremµ is the mobility parameter of the device in (3.9). Extractionof α with
log-log plotting requires knowledge about the exact value of VT . It can therefore not be used
for extractingα and then the threshold voltageVT . Variations about the exactVT value lead
to bent curves in the logID vs. log(VGS − VT ).
Fig. 3.23 shows two logID vs. log(VGS −V ∗
T ) plots for one single device where threshold
voltages ofV ∗
T = 1 V and of -1 V have been assumed. The actualID curve has a threshold
voltage ofVT = 1 V and a power factorα = 3. The left plot shows a curve with a slope of
three above thex value of approximately 0.3 and a steeper slope below that value. The latter is
due to the interaction between the above-threshold and the subthreshold current. The second
plot has been calculated with an anticipated threshold voltage of -1 V and does not show a
linear shape. This result demonstrates that the anticipated threshold voltage affects extraction
of the power factorα.
−8.0
−7.5
−7.0
−6.5
−6.0
−5.5
−5.0
−4.5
−4.0
−3.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4
log(VGS − V ∗
T )
logI D
V ∗
T = 1 V
V ∗
T = −1 V
Fig. 3.23: Extraction of the power factorα for ID ∼ (VGS − VT )α. TheV ∗
T values are used inthex axis calculations.
3.3. Popular Procedures for Parameter Extraction 63
Unified Extraction Method
An analytic approach for both polycrystalline and amorphous TFT transistors calledUnified
Extraction Method(UEM) has been proposed by Estrada et al. in [56]. The method was
originally developed for a-Si TFTs [57] and defines an extraction functionH such that
H(VGS) =
VG∫
0
IDSat(VGS)dVGS
IDSat≈ VG − VT
α + 1, (3.75)
Here,IDSat(VGS) = K(VGS − VT )α, K is a conductance parameter, andα is an empirical
power factor. An n-type transistor andVG > VT is assumed in the following discussions.
The procedure consists of the following steps:
1. ComputeH(VGS) from measuredIDSat(VGS) characteristics.
2. Fit a line toH(VGS) and extract values forα andVT from the slope and the intercept
point ofH with theVGS axis.
3. Calculate the conductance parameterK according toK = IDSat/(VGS − VT )α.
The method can also be extended to polycrystalline silicon TFTs (Psi-TFT) by translating
the parameters used in (3.75) to parameters of Psi-TFTs. Details of the process are given in
[56]. The method is also useful in the calculation of the channel-length modulationλ and
series resistanceR = RS + RD (RS/RD is the source/drain-side series resistance). In [46],
UEM4 has also been used for extracting parameters for pentacene-based devices in bottom-
gate configuration. The method also accounts for constant and diode-like contact resistances.
Details about the extraction scheme can be found in [46].
An alternate way of correctly deriving the threshold voltage and power factor is demon-
strated in Section 4.3.2.
3.3.3 Parameter Fitting
As an alternative to an analytic extraction, fitting procedures can be used for deriving model
parameters. Such schemes employ an optimization engine to find a feasible set of parameters
to describe given output characteristics. Usually, the least-squares sum of the difference be-
tween model prediction and original data is used for measuring the quality of a fit [25, 86]. In
contrast to the graphics-based and analytic procedures described earlier, parameter fitting can
be applied to any model with a valid analytical description.However, the fitting engine needs
initial values for the parameters to extract. Another drawback of parameter fitting is that the
4Later in [46], UEM was renamed toUnified Model and parameter Extraction Method(UMEM).
64 Chapter 3. OFET Modeling for Circuit Simulation
solver could find a local minimum or a physically incorrect set of parameters. The interested
reader is referred e.g. to [87] for a discussion of optimization algorithms.
Discussion of Parameter Fitting
Analytical extraction generally requires special measurement setups and knowledge on feasi-
ble models to use in order to derive model parameters. Parameter fitting does not depend on
such setups and is more general. However, extraction problems often consist of many param-
eters to find. This situation complicates parameter fitting as extraction engines often get stuck
at local minima in multidimensional fitting problems. Moreover, the extraction process needs
a sensible starting point for the extraction. Nevertheless, a numerical solver is far easier to
implement in computer software than an analytical or graphical extraction scheme.
3.4 Automation of Modeling
For the users of circuit simulation in the optimization of OFET devices, automatic parameter
extraction is important. Each time a new device generation is introduced, transistor models
have to be generated so that automation of the modeling process is desirable. Automation
takes place in the form of dedicated modeling tools and should include one or more of the
following features:
2 Data Management– Large-scale measurement series need to be managed.
⊲ From the measurement sets, statistically meaningful parameters need to be ex-
tracted.
⊲ Additional data describing the actual measurements must accompany the measure-
ment data in order to facilitate backtracking of measurement data and extraction
results. This kind of data includes e.g. the name of the sample from which mea-
surements were taken, geometrical dimensions of the devices, date of measure-
ment, operator, etc.
2 Selection tools– The most appropriate modeling approaches for given outputcharacter-
istics need to be identified. This requires tools which aid inselecting the most suitable
model for givenID-VGS characteristics. For example, theVSat method (which will be
presented in Chapter 4) can assist in selecting appropriatemodel types by plotting the
VGS dependence of the principal parametersKP , VT , andλ.
2 Availability of different modeling approaches– Modeling tools should provide different
approaches for modeling so to allow users to try out different model types and extrac-
tion schemes. This can be handled by providing generic modeling interfaces where
3.4. Automation of Modeling 65
dedicated model generators can be linked in. These generators can e.g. contain sophis-
ticated graphical user interfaces or capabilities for dataanalysis.
2 Collaboration with Circuit Characterization Tools– The models are primarily used in
circuit simulation of reasonable circuits like logic gates. Therefore, it is desirable to
embed modeling tools in the circuit characterization environment. In this way, time-
consuming integration of model data into circuit simulations can be avoided.
3.4.1 Existing Tools
There are numerous tools for extracting parameters of transistor models. The degree of au-
tomation in these tools ranges from providing an input mask where graphical the extraction of
the parameters can be done by the users to fully automated extraction procedures.
General-purpose extractors like the commercial tool Synopsys Aurora [88] consist of a
configurable solver and provide a script-based computationengine as well as a graphical user
interface. In the case of Aurora, parameters are extracted by curve fitting with a Levenberg-
Marquardt solver using constraints. The tool allows the users to carry out the extraction in
a series of steps. In each step, a set of parameters to optimize and default values for other
parameters can be defined. Setups like the following are possible: A coarse version of the
threshold voltageVT is extracted in the first extraction step usingID −VGS measurements and
a sensible range forVT . In the next step, the device mobility is extracted. Finally, a general
fit uses previously extracted parameter values as starting points and centers the parameters at
the minimum error between model output and measured curves.Tools like Aurora do not pro-
vide data-management capabilities or direct links to circuit characterization tools. Moreover,
appropriate models have to be selected by inspecting the error between modeling results and
original data.
Some SPICE simulators (e.g. Synopsys Star-Hspice [26] or Tanner T-Spice [68]) include
configurable optimizers which can be used for fitting the curves. These optimizers are con-
trolled by use of special statements in the textual netlists. Tools like Cadence/OrCAD PSpice
[89] or Synopsys SaberDeveloper include graphical front-ends which can be used for a graph-
ical fit of the curves. The simulators are directly linked to circuit characterization tools and
carry out the actual simulations needed in the characterization process. However, they do not
provide data management or convenient selection of appropriate models.
More specialized extractor tools like AIM-EXTRACT [90] provide graphical user inter-
faces and external fit programs for dedicated models. These external fit programs are con-
figured with text files containing references to the requiredmeasurement data and parameter
setups. In AIM-EXTRACT, the parameters are extracted by an undisclosed multi-step plan.
The drawback of the extraction plan is that the fitting results depend on the input parameters.
66 Chapter 3. OFET Modeling for Circuit Simulation
Experiments done by the author of this work revealed that e.g. the initially given thresh-
old voltage is used in calculations within subsequent parameter extractions inside the model
extractor for Psi-TFT devices. The tool is highly specialized because it can only extract pa-
rameters of certain models. Moreover, it does not provide data management or assistance in
selecting appropriate models.
The commercial package Agilent IC-CAP [91] provides a framework for model extrac-
tion. The tool centers on the management of device and circuit characteristics and provides
modeling, management as well as control of measurement instruments, and simulation facili-
ties. All processes can be automated using a built-in control language. Modeling complexity
ranges from the extraction of parameters of primitive models to models described by SPICE
netlists. IC-CAP collaborates with external simulators inorder to test the accuracy of ex-
tracted model parameters or to characterize a circuit usingcircuit simulations. The simulators
are integrated via an open simulator interface. IC-CAP already includes a large set of models
and specialized extraction procedures for the derivation of their parameters.
3.4.2 Discussion
In summary, tools for circuit-level transistor modeling are either very general or specialize on
certain models. The general tools can be configured very flexibly but specialized modeling
tools provide more convenient extraction schemes. With theexception of IC-CAP, none of the
above-mentioned tools provides the analysis capabilitiesneeded for the extraction schemes
presented in Section 3.3. Conversely, the commercial tool IC-CAP provides both very gen-
eral and highly specialized extraction schemes in one software package. However, all tools
investigated in this section lack the treatment of dedicated OFET models or sophisticated data
management.
3.5 Chapter Summary
The following aspects of OFET modeling were discussed in this chapter:
2 Different charge-transport mechanisms in OFETs are currently under debate. Many
issues need to be resolved in order to fully understand the inner workings of organic
transistors. Modeling is complicated by the fact that different OFET technologies exist,
where the availability of many materials and manufacturingmethods leads to various
effects which have to be accounted for.
2 Owing to the early stage in the process of understanding charge transport in organic
semiconductors, many modeling approaches for OFETs are based on well-known mod-
els derived for more traditional semiconductor technologies like crystalline silicon or
3.5. Chapter Summary 67
thin-film transistors. Other models sacrifice a physical basis in favor of accurate mod-
eling, e.g. for simulation of analog circuits. One model with a true OFET-related phys-
ical basis is the model of variable range hopping (VRH). Modeling of capacitances and
stress effects is also still in the beginning. Only one modelpresented in this chapter
honors stress effects by introducing an RC network in order to introduce hysteresis in
the switching behavior of transistors.
2 Themodel quality chart(MQC) was defined in this chapter in order to allow ratings and
comparisons of the various models with respect to accuracy,modeling of capacitances,
compactness, parameter extraction and stress effects. OFET models were then analyzed
by use of MQC tables. Table 3.12 lists the results obtained bythe discussion of these
models.
Table 3.12: MQC values for models presented in this work.Requirement Level-1 Psi-TFT a-Si TFT VRH Table Dresden
& contacts
Accuracy bad to good good good good goodmedium
Capacitance – – – good good –modelingCompactness good good good good bad bad
Parameter good medium bad medium not mediumextraction neededStress Effects – – – – – medium
2 Accuracy in Table 3.12 has been rated according to the data sets used for developing the
respective models. As will be shown in Section 4.3.5 and Section 4.3.6, models have
their peculiar shortcomings when dealing with different device technologies. Therefore,
it is not possible to select one modeling approach equally useful for all types of devices.
Extraction methods are normally centered on finding the best-fitting parameters for a
given set of parameters and a given model. Whether the model matches the data can
only be seen at the end of the extraction procedure. From the user’s point of view, it
would be desirable to have this information before any lengthy extractions are carried
out. In this respect, the traditional question which set of parameters best maps measured
curves for a given model translates into the question which model potentially maps the
given curves.
68 Chapter 3. OFET Modeling for Circuit Simulation
2 There exist many tools and measurement procedures for deriving parameters of popular
models. However, these tools require skilled users and appropriate data sets. In order to
provide maximum use, a generic framework for analyzing the performance of OFETs
in logic circuits should assist users in the derivation of appropriate model sets. Here,
features like data management, selection of best-fitting models, implementation of user-
friendly fitting approaches, and collaboration with the circuit characterization part of the
framework are important. Existing extraction tools do not provide these characteristics.
The issues of extracting reasonable threshold voltages andselecting proper models will
be addressed in the following chapter, where a novel modeling and analysis tool namedVSat
method is discussed. Chapter 6 then contains a description of a computerized methodology
for flexible transistor modeling and characterization of OFET-based logic circuits.
69
Chapter 4
VSat Method
In this chapter, a novel approach to extracting model parameters of transistors is detailed. The
method is based on two observations made by the author of thiswork.
The first observation is that most models presented in Section 3.2 are variations of the
Level-1 model. In these models, constant parameters are replaced by variable parameters,
which e.g. depend on the gate-source voltage. The idea of thenovel extraction method is to
decompose a measured set of output characteristicsID vs. VDS into individual output curves,
one for each givenVGS value. The basic parametersVT , KP , andλ of the Level-1 model are
then calculated for each of these curves. By plotting the extracted parameters vs.VGS, the
best-fitting model type can be identified because the different models have characteristicVGS
dependences of their parameters.
The second observation is that the three-dimensional problem of extracting the basic pa-
rametersVT , KP , andλ for a single output characteristic can be reduced to a one-dimensional
problem of findingVT and calculatingKP andλ from it. VT can be determined by searching
the transition point between the linear and the saturation region, i.e. the saturation voltage
VSat, and calculatingVT from the relationshipVSat = VGS − VT . Owing to the role ofVSat in
the extraction process, the extraction method has been named VSat method.
The extraction procedure and its application in transistormodeling are detailed in the
following sections. First, the extraction scheme is described. Then, two transistor models are
presented which directly integrate theVSat method. Finally, experimental results showing the
application of the extraction procedure and novel modelingtechniques are discussed.
70 Chapter 4. VSat Method
4.1 Extraction based onVSat Method
Automatic extraction of model parameters with theVSat method is based on the following
assumptions:
2 The model parameters depend onVGS.
2 Individual ID vs. VDS curves with constantVGS can be covered by Level-1 modeling
from (3.1) to (3.3).
2 Appropriate models for given characteristics can be found by plotting the basic Level-1
parametersKP , VT , andλ vs. VGS
TheVSat method relies on the determination of the saturation voltageVSat, i.e. the drain-
source voltage of anID vs. VDS curve where the transition from the linear to the saturation
region takes place.VSat can be determined by varying a guess of it in the availableVDS range,
calculatingVT , KP , anλ from the guessedVSat, and observing the mean-square error between
the resulting Level-1 model and the measurement data or by employing a one-dimensional
optimization routine.
The values necessary for calculating the model parameters are shown in Fig. 4.1. They
are obtained as follows: FromVSat and the respective drain currentIDsat, the maximum drain
voltageVDMax and the respective drain currentIDMax, the parametersKP andλ can be de-
rived using the following equations.
VT = VGS − VSat, (4.1)
f =
∣
∣
∣
∣
IDMax − IDSat
VDMax − VSat
∣
∣
∣
∣
, (4.2)
|IDS0| = |IDSat| − f · |VSat|, (4.3)
KP = 2|IDS0|/V 2Sat, (4.4)
λ =f
|IDS0|. (4.5)
Here,f is the slope ofID betweenVSat andVDMax, all other parameters have their usual
meaning. Absolute values are used so that positive values are guaranteed for both n-type and
p-type transistors.f can be calculated from theID values atVDMax andVSat. Alternatively,
f can also be derived by calculating the linear regression of theID points betweenVSat and
VDMax. The latter procedure is more robust against measurement noise as more points are used
in the calculation of the slope.IDS0 is the drain current in the saturation region withλ = 0.
It can be used to calculateKP by exploiting the relationshipIDS0 = 12
WL
KP V 2Sat. λ can be
4.1. Extraction based onVSat Method 71
derived fromIDMax − IDSat = 12
WL
KPV 2Sat · λ · (VDMax − VSat) which leads tof = λ · IDS0.
VSat
IDS0
IDSatslopef
I ′
D
I D
VDS
IDMax
VDMax
Fig. 4.1: Important points on theID vs. VDS curve for calculating model parameters accordingto theVSat method. The dashed curveI ′
D denotes the drain current forλ = 0. VGS is constantfor the curve.
Fig. 4.2 shows a plot of the mean-square error vs. the guessedsaturation voltageVSat
of two different simulations1. In the underlying experiment, drain currents were simulated
with a VDS increment of 0.1 V and 1.0 V. Then,VSat was guessed by varying the unknown
value between 3 V and 10 V with a step size of 0.1 V. The mean-square error was calculated
according to
ε =1
n
n∑
i
[ID,m(VDS,i) − ID,s(VDS,i, VSat)]2 . (4.6)
Here,n is the total amount of measured points,ID,m is the measured or interpolated drain
current (indexm for “measured”).ID,s is the drain current according to the Level-1 model
and the parameters extracted with theVSat method (indexs for “simulated”).
Both curves show minima atVSat ≈ 8.4 V. The curve labeled “original data withVDS
increment of 0.1 V” is smoother. The other curve has local minima which can cause an
optimizer to get stuck at these points (e.g.VSat = 6 V). The plot also shows that the resulting
parameter accuracy depends on the sampling density of the measuredID points. Moreover,
the presence of local minima complicates the application ofmany numerical optimization
methods. However, the optimal solution can be found by the above-mentioned procedure of
varying VSat in a fixed interval in steps of e.g. 0.1 V and selecting theVSat value for the
minimum mean-square errorε.1Level-1 model, simulation data:β=10 nA/V2, VT = −6.4 V, λ = 0.01 1/V, VGS = 2 V.
72 Chapter 4. VSat Method
0.0
0.5
1.0
2.0
2.5
3.0
3.5
3 4 5 6 7 8 9 10
4.0
1.5
guessedVsat [V]
× 10−15ε
[A2]
original data withVDS increment of 1.0 V
original data withVDS increment of 0.1 V
Fig. 4.2: Dependence of the modeling error on the measurement grid.
The reader is referred to Section 4.3 for a demonstration of theVSat method with measured
output characteristics.
Discussion
TheVSat method approaches modeling in a mixture of fitting and analytical methods. First,
the threshold voltageVT is derived by a numerical extraction of the saturation pointof anID
vs. VDS plot. Then, the other parametersKP andλ are analytically calculated fromVT . This
approach reduces the three-dimensional fitting problem to aone-dimensional search which
can be carried out fully automatically.
Application of theVSat method entails using the whole range of drain-source voltages
VDS. Therefore, effects introduced by series resistances affect the extracted parameters, e.g.
reduce effective voltages due to voltage drops across the series resistors. Existing methods
of extractingVT therefore often resort toID vs. VGS curves with small drain-source voltages
VDS below 1 V.
TheVSat method generates intermediate parameters used to identifyappropriate modeling
approaches. For example, the Level-1 model yields parameters which are independent of
VGS while the threshold voltageVT in the Psi-TFT model linearly depends onVGS and on
a conductance factorKP with a power-law dependence (see Section 4.3.2 for more details).
By plotting them againstVGS, the parameters aid in the selection of appropriate modeling
approaches because the parameter curves in the individual models have characteristic shapes
4.2. Modeling based onVSat Method 73
with respect toVGS.
4.2 Modeling based onVSat Method
TheVSat method can be used as the first step of a two-step extraction procedure similar to the
intermediate model approachdeveloped by Kondo and co-workers to extract parameters of
MOSFET transistors [92].
In the intermediate model approach, model parameters are extracted by a two-step con-
cept. In the first step, intermediate parameters are extracted from measured I-V data. In
a second step, these intermediate parameters are transformed into parameters of the target
model. Splitting the extraction process into two steps allows device-independent extraction
routines for the intermediate parameters. Mapping the intermediate parameters to the parame-
ters of the target model is then device-dependent. Kondo andcolleagues emphasize that once
an acceptably accurate intermediate model has been established, model designers only need
to derive a mapping procedure for the parameters of the target model.
The original approach by Kondo and colleagues is used to extract one set of parameters
for a complete set of output characteristics. It works with the subthreshold and linear region.
Conversely, theVSat method is used to derive distinct sets of Level-1 parametersfor individual
above-threshold curves ofID vs.VDS measured at constantVGS values. The distinct parameter
sets are then related to extract a common parameter set for all measuredVDS andVGS values.
In the following, two modeling approaches based on data derived by theVSat method will
be discussed: a table-based model and an analytical model called Linvar model. The latter
model utilizes the concept of intermediate parameters.
4.2.1 VSat-Type Table-Based Model
TheVGS-dependent parametersVT , KP , andλ can be directly recorded in a table generated
by theVSat method. During circuit simulation, the model parameters are then taken from this
table or are interpolated / extrapolated from existing values. A table model has been written
in this work in XSPICE [93]. The reader is referred to Section6.3 for a demonstration of
its application. This type of model is easy to implement and does not require sophisticated
compression equations like the model in [31]. Moreover, theparameter table does not store
measurement values like other modeling approaches do. Instead, theVGS-dependent param-
eters of the Level-1 model are tabulated vs. the gate-sourcevoltage. With this approach,
parameters of the model can be changed without the need to store a new set of output char-
acteristics for the table model. On the other hand, the tablemodel only works correctly if the
individual I/V curves can be approximated by Level-1 modeling. This is not possible when
74 Chapter 4. VSat Method
e.g. diode-like contact effects are present.
Discussion
Table 4.1 provides ratings for the table-based model with respect to the model quality chart
presented in Section 3.1. Accuracy was rated as good becausethe model can map output
characteristics when the individual curves are Level-1-shaped. Modeling of transistor capac-
itances or stress effects is not included. Compactness has been rated as bad because many
values are needed. In the parameter extraction, only theVSat method is necessary. Therefore,
the parameter extraction has been rated as good.
Table 4.1: MQC forVSat-type table-based model.Requirement Rating
Accuracy goodCapacitance Modeling not includedCompactness badParameter Extraction goodStress Effects not included
4.2.2 Linvar Model
The VGS-dependence of the extracted parameters can be approximated by analytical equa-
tions. TheLinvar modelhas been developed in this work to provide such a relationship. The
model parameters are assumed to be variables linearly depending onVGS. Hence the name
Linvar model is used. Other dependences (polynomial, exponential) were analyzed in [94],
but these functions add more parameters and therefore reduce the compactness of the model.
Experimental studies on OFETs based on poly-(3-hexyl)thiophene (P3HT) (see Section 4.3.2)
showed that a linear dependence represents a good compromise between compactness (num-
ber of parameters) and accuracy (mean-square error with respect to measurements) of the
model.
Model Equations
In the Linvar model, theVGS-dependent parameter sets are mapped to the following functions:
4.2. Modeling based onVSat Method 75
KP (VGS) = KP0 + fk · VGS, (4.7)
VT (VGS) = VT0 + fT · VGS, (4.8)
λ(VGS) = λ0 + fλ · VGS. (4.9)
Assuming n-type devices for the discussion, the equations of the Linvar model are:
1. Cutoff region withVGS < VT :
ID = 0. (4.10)
2. Linear region with0 < VDS < VGS − VT (VGS):
ID = KP (VGS) · W
L
(
VGS − VT (VGS) − VDS
2
)
VDS · [1 + λ(VGS)VDS]. (4.11)
3. Saturation region with0 V < VGS − VT (VGS) < VDS:
ID =1
2KP (VGS) · W
L[VGS − VT (VGS)]2 · [1 + λ(VGS)VDS]. (4.12)
In order to map the existence of a subthreshold or bulk current, a resistorRpar parallel
to the transistor channel is added between source and drain.The resistance value can be
determined using the difference between a measuredID point for zeroVGS and the model
prediction withoutRpar. The resistor can be normalized to a width-independent contribution
using
R′
par = Rpar · Wref , (4.13)
whereWref is the width of the modeled device. The drain-source currentthen becomes
IDS = ID + VDS · R′
par/W. (4.14)
Discussion
The main advantage of the Linvar model is its simplified parameter extraction scheme. The
procedure is especially suitable for automatic extraction. On the other hand, the Linvar model
simply represents a fitting model. Therefore, the parameters do not directly reflect process or
material properties. The model is restricted to devices where the parameters show linear de-
pendence onVGS. The extraction scheme does not take contact resistances atdrain and source
into account. These elements have to be derived beforehand in order to extract meaningful
values forKP , λ andVT .
76 Chapter 4. VSat Method
In Table 4.2, a rating of the Linvar model with respect to the model quality chart pre-
sented in Section 3.1 is shown. Accuracy was rated as medium as the model only matches
a restricted set of device structures. In particular, only devices with linearVGS-dependence
of the parameters are mapped. Capacitance modeling or stress effects are not included in the
modeling. Although the model relies only on a small set of parameters, compactness was
rated as medium because these parameters are only fitting parameters. On the other hand, pa-
rameter extraction is rated as good because easy-to-use fitting parameters are used. Owing to
the application of theVSat method, no starting values are needed for the parameters to extract
and the extraction process is reduced to a one-dimensional search.
Table 4.2: MQC for Linvar model.Requirement Rating
Accuracy mediumCapacitance Modeling not includedCompactness mediumParameter Extraction goodStress Effects not included
4.3 Experimental Results on Transistor Fitting
In the following, experimental results on the analysis of transistor parameters with theVSat
method are presented. First, the characteristic behavior of commonly used transistor models
will be explored. Then, the effect of constant contact resistance is treated. A method is
demonstrated how these parasitic elements can be compensated for in the analysis. Finally,
the application of the Linvar model on measurement curves ispresented.
4.3.1 Analysis of a Level-1 Transistor
The VSat method is based on the Level-1 model (see Section 3.2.1) which provides simple
equations to predict the behavior of transistors. In theVSat method, the saturation voltages
of individualID-VDS curves are extracted. Subsequently, all extracted saturation voltages are
plotted versus their respectiveVGS values. In the case of a Level-1 transistor, a line with unity
slope can be expected becauseVSat = VGS − VT . FromVSat, the threshold voltageVT can
readily be extracted and the other Level-1 parameters are calculated using (4.2) through (4.5).
Fig. 4.3 shows the output characteristics of a Level-1 transistor2, the extracted saturation
voltageVSat as well as the derived parameters process conductanceKP and channel-length2Original model data: p-type transistor,VT =3 V, KP =10 pA/V2, λ= 10 mV−1.
4.3. Experimental Results on Transistor Fitting 77
modulationλ. The threshold voltage has not explicitly been plotted because it can be derived
from the saturation voltageVSat. As expected, the saturation voltageVSat has a slope of one
and intersects the zeroVGS point at−VT . KP andλ are independent of the gate-source bias
and coincide with the given model parameters.
The example shows that theVSat method can well extract a true Level-1 transistor. How-
ever, the extractor needs enough points between the supposed saturation voltage and the maxi-
mum|VDS| in order to safely detect the linearIDS line of the saturation curve. To demonstrate
this requirement, the above transistor is analyzed with theVGS values ranging from 0 to -20 V
in steps of 2 V andVDS also ranging from 0 to -20 V only, but in steps of 1 V. Fig. 4.4 shows
the resulting plot for theVSat curve, the Linvar-model approximation for the parametersKP ,
VT andλ. At |VDS| > 15 V, the curves start to considerably deviate from the expected be-
havior. The data shows that theVSat prediction gets inaccurate forVGS values approaching
-20 V.
4.3.2 Analysis of Model for Polycrystalline TFTs
The TFT model for polycrystalline silicon (Psi-TFT, see Section 3.2.2) is a semi-empirical
model with a physical background [41]. It effectively extends the Level-1 model by adding
a VGS-dependent mobility and a factor for the variation of the saturation voltage (αsat). The
output characteristics as well as extracted curves for a simulated polycrystalline thin-film
transistor3 are depicted in Fig. 4.5.
Level-1 parameters derived from the extracted curves do notdirectly correspond to the
model parameters of the Psi-TFT model. This is due to the modifications of the model with
respect to the original Level-1 model (see Section 3.2.2). In the Psi-TFT model, the satu-
ration voltage is calculated byVSat = αsat(VGS − VT ). Therefore, the slope of the curve in
Fig. 4.5b can be used to deriveαsat ≈ 1.7. From this slope, the threshold voltage is derived
by VT = −VSat(VGS = 0 V)/αsat = 1 V.
With VT andαsat established, the power factormµ for the mobility can be estimated by
plotting logID vs. log(VGS − VT ) for a fixedVDS in the saturation region. The slope of the
log-log curve corresponds to2 + mµ owing toID ∼ (VGS − VT )2+mµ . Fig. 4.5f depicts the
log-log curve. This approach leads to a slope of 3.2, which coincides with2 + mµ. Finally,
µ0 can be obtained by inserting a measured current value into the model equation and solving
for µ0. TheVGS-dependence ofKP in Fig. 4.5c can be used for qualitative examinations. In
the figure,KP displays weakly super-linear behavior which suggests a power factormµ > 1.
Fig. 4.5d showsλ, the parameter for the channel-length modulation. The deviation from
3Model data: µ0 = 1·10−3 cm2/Vs, Cis = 1 · 10−7 F/cm2, VT = 1 V, αsat = 1.7, mµ = 1.2,µs = 1 · 10−11 cm2/Vs, ηi = 3.34,I0 = 1 · 10−13 A, W/L = 1000
78 Chapter 4. VSat Method
a)
−30 −25 −20 −15 −10 −5 0
6.0p
8.0p
10.0p
12.0p
−20 −15 −10 −5 0
b)
5.0m
6.0m
7.0m
8.0m
9.0m
10.0m
11.0m
12.0m
13.0m
14.0m
15.0m
−20 −15 −10 −5 0
−25
−20
−15
−10
−5
0
−20 −15 −10 −5 0
−1.0u
−1.5u
−2.0u
−2.5u
−3.0u
−3.5u
saturation curve
−0.5u
0.0
14.0p
d)c)VDS [V]
VGS=-20 V
VGS=-18 V
VGS=-16 V
VGS= 0 V
KP
[A/V
2]
λ[V
−1]
VGS [V]
VGS [V] VGS [V]
I D[A
]
VS
at[V
]
Fig. 4.3: Plot of important parameters of a Level-1 transistor with p-type behavior:a) output characteristics, b) saturation voltage, c) process conductance, and d) channel-lengthmodulation.
4.3. Experimental Results on Transistor Fitting 79
a) b)
d)c)
−20
−18
−16
−14
−12
−10
−8
−6
−4
−2
−20 −15 −10 −5 0 9.5p
9.6p
9.7p
9.8p
9.9p
10.0p
10.1p
10.2p
10.3p
10.4p
10.5p
−20 −15 −10 −5 0
2.0
2.5
3.0
3.5
4.0
−20 −15 −10 −5 05.0m
6.0m
7.0m
8.0m
9.0m
10.0m
11.0m
12.0m
13.0m
14.0m
15.0m
−20 −15 −10 −5 0
VGS [V]
KP
[A/V
2]
λ[V
−1]
VGS [V]
VGS [V] VGS [V]
VS
at[V
]V
T[V
]
Fig. 4.4: VSat-type extraction with an insufficientVDS range: a) extracted saturation volt-age, b) derived process conductance, c) threshold voltage,and d) channel-length modulation.Dashed lines show the expected curves.
80 Chapter 4. VSat Method
a)
c)
e)
b)
d)
f)
−2.5m
−2.0m
−1.5m
−1.0m
0.0
−50 −40 −30 −20 −10 0
−0.5m
0.0
1.0n
1.5n
2.0n
2.5n
−20 −15 −10 −5 0
0.5n
0.0
5.0m
10.0m
15.0m
20.0m
−20 −15 −10 −5 0−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
0 0.5 1 1.5 2 2.5 3 3.5
0.0
5.0
10.0
15.0
20.0
−20 −15 −10 −5 0
−40.0
−35.0
−30.0
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
−20 −15 −10 −5 0VDS [V]
VGS [V]
VGS [V] log(VGS − VT ) –>
VGS [V]
VGS [V]
I D[A
]K
P[A
/V2]
λ[V
−1]
log(I
D)
[]V
T[V
]V
Sat[V
]
Fig. 4.5: Behavior of a polycrystalline thin-film transistor: a) output characteristics,b) saturation voltage, c) process conductance, d) threshold voltage, e) channel-length mod-ulation, and f) logarithmic drain current.
4.3. Experimental Results on Transistor Fitting 81
constant behavior near zeroVGS can be attributed to the influence of the subthreshold current
according to (3.12).
The plots from Fig. 4.5 can be used to check whether the Psi-TFT model matches a mea-
sured device. If the log-log plot ofID vs. VGS −VT does not yield a straight line, the Psi-TFT
model does not correctly map the output characteristics of the respective device.
4.3.3 Effect of Contact Resistance on Level-1 Model
The ideal behavior of the Level-1 model can be weakened by thepresence of contact resis-
tance at the interface between the source/drain electrodesand the channel region. Contact
resistance is often encountered e.g. in bottom-gate bottom-contact transistors where the elec-
trodes disturb the formation of the semiconductor film and trap states occur. These trap states
lead to diode-like contact resistance which can be difficultto model. Diode-like resistances
also occur when the work functions of the electrode materialand the semiconductor in the
transistor channel are not aligned.
Constant resistors at the source and drain electrodes are more tractable form of contact
resistance. Their presence in a Level-1-type transistor has already been discussed briefly in
Section 3.3.1. At this point, their influence on extracted parameters will be analyzed. A device
model according to Fig. 4.6 will be assumed.RDC andRSC represent the drain-side and
source-side contact resistances whileM maps the ideal Level-1 transistor. TheVSat extractor
treatsM as a unit withRDC / RSC and derivesVGS-dependent Level-1 parameters for the
combined device. The extraction results are effective parameters that can be used to see how
contact resistance affects the output characteristics.
GATE
DRAIN
SOURCE
RSC
RDC
M
Fig. 4.6: Schematic of a transistor with contact resistances at drain and source.
In the analysis,RDC andRSC shall be varied independently and the ideal transistorM
shall have the same model parameters as in Section 4.3.1. Fig. 4.7 shows extraction results
82 Chapter 4. VSat Method
for differentRDC values.RDC alone (RSC = 0 Ω) strongly influences the saturation voltage
as can be seen from Fig. 4.7a. In the plot, theVGS-dependent saturation voltage is shown. The
data demonstrates that small values ofRDC in the range of 100 kΩ do not noticeably affect
transistor behavior for the given device. However, higherRDC values shift the saturation point
to more negative values.
A VSat-type parameter extraction shows that the drain-side resistor strongly influences
(viz. shifts)VT andKP . KP decreases withRDC . Consequently, increasingRDC also de-
creases the attainable current as demonstrated by Fig. 4.7d. The effect ofRDC will also be
more pronounced for increasing|VGS| owing to the fact that the drain current also increases
as well as the voltage drop atRDC .
The source-side contact resistance (RSC) can also be varied withRDC being removed
(RDC = 0 Ω). In this case, the maximum drain current is affected while the saturation points
effectively keep unchanged as long asRSC does not get too large. At some resistance value,
RSC will start to dominate theID-VDS curve. This can be seen from the graphs in Fig. 4.8.
In conclusion, a noticeable resistance at the drain contactwill influence the saturation
voltageVSat, the process conductanceKP and on-currents. A noticeable resistance at the
source contact on the other hand will influence the process conductanceKP , the channel-
length modulationλ and both the on/off current.
4.3.4 Compensation of Contact Resistance
TheVSat method only measures effective parameters. It does not separate the contributions of
contact resistors due to the nonlinear interaction betweenthe transistor andRDC /RSC . These
resistances can be determined by a resistance measurement like the potential profiling (see
Section 3.3.1). If the approximate values are known they canbe compensated for by placing
additional negative resistors (RCD andRCS) in series to the transistor during simulation as
shown in Fig. 4.9. At these points in the device setup, they neutralize the effect of the contact
resistances.
The presence ofRCD andRCS leads to equal potentials at DRAIN and DP as well as
SOURCE and SP. In a computer simulation, the parameters of transistorM can now be ex-
tracted using the usual methods:
1. Obtain effective parameters or a table-based model of thetransistor operating under the
influence of the contact resistances.
2. Derive the contact resistances by measurement.
3. Neutralize the contact resistance by a setup equivalent to Fig. 4.9. With this setup, the
drain-source voltage and gate-source voltage across transistor M are equivalent to the
4.3. Experimental Results on Transistor Fitting 83
a) b)
d)c)
9.0m
9.5m
10.0m
10.5m
11.0m
−70.0
−60.0
−50.0
−40.0
−30.0
−20.0
−10.0
0.0
1.0p
2.0p
3.0p
4.0p
5.0p
6.0p
7.0p
8.0p
9.0p
10.0p
10.0n
1.0u
10.0u
0.0 2.0M 4.0M 6.0M 8.0M 10.0M0.0 −5.0 −10.0 −15.0 −20.0
−20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0
0.1u
1.0 MΩ0.1 MΩ
RDC= 0.0 MΩ
2.0 MΩ5.0 MΩ
10.0 MΩ
KP
[A/V
2]
λ[V
−1]
VS
at[V
]
RDC [Ω]VGS [V]
VGS [V] VGS [V]
I D[A
]
Fig. 4.7: Behavior of important transistor parameters withrespect to different values for thedrain-side contact resistance: a) saturation voltage, b) process conductance, c) channel-lengthmodulation, d) on/off current.
84 Chapter 4. VSat Method
a) b)
c) d)
2.0p
3.0p
4.0p
5.0p
6.0p
7.0p
8.0p
9.0p
10.0p
2.0m
3.0m
4.0m
5.0m
6.0m
7.0m
8.0m
9.0m
10.0m
11.0m
10.0n
0.1u
1.0u
10.0u
−30.0
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
−20.0 −15.0 −5.0 0.0 −10.0 −20.0 −15.0 −10.0 −5.0 0.0
−20.0 −15.0 −10.0 −5.0 0.0 0.0 2.0M 4.0M 6.0M 8.0M 10.0M
10.0 MΩ
RSC = 0.0 MΩ0.1 MΩ1.0 MΩ
5.0 MΩ2.0 MΩ
VS
at[V
]
VGS [V] VGS [V]
KP
[A/V
2]
λ[V
−1]
VGS [V] RSC [Ω]
I D[A
]
Fig. 4.8: Behavior of important transistor parameters withrespect to different values of thesource-side contact resistance: a) saturation voltage, b)process conductance, c) channel-length modulation, and d) on/off current.
4.3. Experimental Results on Transistor Fitting 85
DRAIN
GATE
DP
SP
SOURCE
MVDS
RDC
RCD = −RDC
RSC
RCS = −RSC
VGS
Fig. 4.9: Transistor with resistors neutralizing the contact resistances.
voltage drop between the terminals DRAIN and SOURCE and GATEand SOURCE,
respectively.
Results of the procedure are demonstrated in Fig. 4.10. The figure depicts extracted curves
vs. VGS for a device simulated withRSC = 2 MΩ, noRDC , and various compensation resistors.
The method of resistance compensation can also be used to determine the contact resis-
tancesRSC andRDC . The approach exploits the fact that the channel-length modulationλ
is mainly affected byRSC and the saturation voltageVSat only by RDC . By exploiting these
relationships,RDC can be determined by bringingVSat to a straight line through varyingRCD
andRSC by bringingλ to a straight line through varyingRCS.
86 Chapter 4. VSat Method
a)
c) d)
b)
5.0m
10.0m
15.0m
20.0m
25.0m
30.0m
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
6.0p
7.0p
8.0p
9.0p
10.0p
11.0p
12.0p
13.0p
14.0p
15.0p
10.0n
1.0u
10.0u
−20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0
−20.0 −15.0 −10.0 −5.0 0.0 0.0 0.5M 1.0M 1.5M 2.0M 2.5M 3.0M
0.1u
RSC = 2 MΩ
RSC = 2 MΩ
RSC = 2 MΩ
RSC = 2 MΩ
3.0 MΩ2.0 MΩ1.0 MΩ0.1 MΩ
RCS = 0.0 MΩ
λ[V
−1]
VGS [V] VGS [V]
VGS [V] RSC [Ω]
VS
at[V
]
I D[A
]K
P[A
/V2]
Fig. 4.10: Behavior of important transistor parameters with respect to different values ofthe source-side compensation resistance: a) saturation voltage, b) process conductance,c) channel-length modulation, and d) on/off current. The contact resistance at the sourceelectrode isRSC = 2 MΩ.
4.3. Experimental Results on Transistor Fitting 87
4.3.5 Analysis of a PDHTT Transistor
Fig. 4.11 shows theID−VDS curve of a poly(3,3”-dihexyl-2,2’:5’,2”-terthiophene) (PDHTT)
transistor and the parameters extracted by theVSat method. I/V data was taken from [95]. The
device has a channel width of 10,000µm and a channel length of 10µm.
The resulting curves show that the saturation voltage decreases linearly between gate volt-
ages of -4 V and -24 V. At gate voltages below -24 V,VSat begins to saturate. This behavior
can be attributed to|VGS| approaching max.|VDS|, a voltage region where theVSat method is
no longer reliable (see Section 4.3.1). The process conductanceKP sharply increases between
gate voltages of 0 and -5.0 V and then slowly degenerates. At gate-source voltages below -24
V, it starts to rise again. This latter rise might also be due to the difficulties in extracting
the correct saturation voltages at theseVGS ranges. The decline ofKP between gate-source
voltages of -6 V and -24 V might be due to the presence of source-side contact resistance.
Moreover, the shape ofVSat andKP implies that Psi-TFT or Linvar modeling is not neces-
sary for the transistor. Instead, theVGS-dependent development of the parameters indicates a
Level-1 model including contact resistances. However, forgate-source voltages above -5 V,
the Level-1 model will fail and produce current values far inexcess of the measured values
because a Level-1 model would not map the decline of the process conductance parameter
KP between -5 V and 0 V. When using a source-side compensation resistor ofRCS = -400
kΩ, KP can be stabilized to 21 pA/V2 for VGS < -10 V with VT = -0.7 V,λ = 0.001 V−1. The
compensation resistor indicates a source-side contact resistance ofRSC = −RCS = 400 kΩ. It
should be noted that such a Level-1 model including a source-side resistor will nonetheless
fail to match device behavior for|VGS| < 5 V.
4.3.6 Modeling of a P3HT Transistor
In this section, the drain current of a P3HT transistor is analyzed using theVSat method and
modeled with the Linvar approach. The device characteristics were obtained from activities
within the research project POLITAG4. The results of the measurements, extractions, and
approximations with the Linvar model are shown in Fig. 4.12.Solid lines mark measured
I/V curves or parameters extracted with theVSat method. Dashed lines and/or cross markers
indicate approximations with the Linvar model. The plots show that the Linvar model sup-
plies a reasonably good fit. Model parameters in the Linvar model wereKP0 = 8 pA/V2,
fk = -2 pA/V3, VT0 = 2.4 V, fT = 0.2 V, λ0 = 5 mV−1, fλ = 0 V−2. In order to better ap-
proximate the drain current at zero gate-source voltage, a normalized parallel resistor with
4The devices were fabricated in top-gate structure by lithographic structuring of gold electrodes. Spin-coatingwas used to deposit the semiconductor. Detailed specifications of the fabrication process were not provided bythe device manufacturer, a commercial source participating in the research project POLITAG. This project wasfunded by the German Ministry for Education and Research (BMBF) under the ID 01BI150.
88 Chapter 4. VSat Method
b)
d)
a)
c)
−6.0u
−5.0u
−4.0u
−3.0u
−2.0u
−1.0u
1.0u
0.0u
0.0
5.0p
10.0p
15.0p
20.0p
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
0.05
0.20
0.25
0.30
0.35
0.40
0.15
0.10
−30.0 −25.0 −20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0 0.00
−7.0u
25.0p
−20.0 −25.0 −30.0 −15.0 −10.0 −5.0 0.0 −30.0 −25.0 −20.0 −15.0 −10.0 −5.0 0.0
-30.0 V-27.5 V-25.0 V
VGS = 0.0 V
-22.5 V
-20.0 V
-17.5 V
-15.0 V
-12.5 V-10.0 V
VGS [V] VGS [V]
VDS [V] VGS [V]
λ[V
−1]
I D[A
]K
P[A
/V2]
VS
at[V
]
Fig. 4.11: Extraction of relevant parameters for a PDHTT transistor with channel widthW = 10 mm and channel length L = 10µm: a) output characteristics (taken from [95]), b)saturation voltage, c) process conductance, and d) channel-length modulation.
4.4. Chapter Summary 89
R′
par = 10 TΩm was introduced between source and drain of the transistor (effective value
Rpar = 1.67 GΩ). This parallel resistor can be attributed e.g. to bulk conductance of the de-
vice.
Alternatively, the device can be approximated using the Psi-TFT model. When apply-
ing the procedure described in Section 4.3.2, the followingmodel set is obtained by calcu-
lations: Cis = 1 · 10−7 F/cm2, µ1 = 2.5 · 10−5 cm2/Vs, VT = 2.9 V, αsat = 0.8, mµ = 0.886,
λ = 0.005 V−1. Here,Cis andµ0 are arbitrarily interchangeable5. Apart from subthreshold
behavior, which has been neglected in this example, the parameter set for the Psi-TFT model
shows good agreement with the experimental data (not depicted in Fig. 4.12a). Here, the Psi-
TFT model performs even better than the Linvar model. This better agreement is at the cost
of a more challenging extraction procedure, however.
4.3.7 Conclusions
Section 4.3 deals with the modeling of organic transistors.The analysis is based on theVSat
and Linvar methods of parameter extraction. In principle, theVSat method indicates appro-
priate models for a particular device by showing the linearity and slope of theVGS-dependent
parameters.
The findings in Section 4.3.5 and Section 4.3.6 show that different transistors can consid-
erably differ in behavior. Therefore, it is difficult to find model equations which are suitable
for a wider range of transistors. The dependence of model parameters could be approximated
by fitting polynomials. This technique was analyzed in [94] but polynomials still fail to cor-
rectly map theKP behavior presented in Section 4.3.5. Moreover, mere fittingpolynomials
do not comply with the requirement of compact device models derived in Section 3.1 because
numerous and obscure fitting parameters are introduced. TheLinvar model is also a fitting
model but uses only as few parameters as possible.
4.4 Chapter Summary
In this chapter, a methodology for extracting parameters oftransistor models in atwo-step
approachwas described. In afirst step, the saturation voltage of individual output charac-
teristicsID vs. VDS at fixedVGS values are extracted by a one-dimensional search routine.
The methodology is centered on the derivation of the saturation voltage. Hence, it is called
VSat method. OnceVSat has been obtained, Level-1 parameters are calculated analytically for
the individual output characteristics. The advantage of this approach is that no user interac-
5Due to the fact that information on the relative permittivity and insulator thickness of the device was notavailable, the default value has been chosen forCis.
90 Chapter 4. VSat Method
a) b)
c) d)
extractionapproximation
extractionapproximation
extractionapproximation
extractionapproximation
0.0
5.0p
10.0p
15.0p
20.0p
25.0p
30.0p
35.0p
40.0p
45.0p
50.0p
55.0p
−6.0u
−5.0u
−4.0u
−3.0u
−2.0u
−1.0u
0.0
1.0u
approximationmeasurement
−20.0
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
−4.0
−2.0
5.0m
10.0m
15.0m
20.0m
25.0m
30.0m
35.0m
40.0m
−30.0 −25.0 −20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0
−20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0
VGS = 0 V
VGS = -4 V
VGS = -8 V
VGS = -12 V
VGS = -16 V
VGS = -20 V
I D[A
]
λ[V
−1]
VGS [V]VDS [V]
VGS [V] VGS [V]
KP
[A/V
2]
VS
at[V
]
Fig. 4.12: Extraction of relevant parameters for a P3HT transistor with channel widthW = 6 mm and channel length L = 10µm: a) output characteristics, b) saturation voltage,c) process conductance, and d) channel-length modulation.Measured and extracted data areshown by solid lines, approximations by the Linvar model areshown by dashed lines and/orcross markers.
4.4. Chapter Summary 91
tion is necessary regarding initial values or parameter bounds for the parameter extraction.
Therefore, the method can be carried out fully automatically.
By observing theVGS-dependent shapes of the basic Level-1 parameters,viable modeling
approaches(e.g. Psi-TFT, Level-1 modeling, etc.) can be identified andthe respective models
can be applied in thesecond step. Currently, the only models directly using all of the interme-
diate Level-1 parameters are aVSat-type table model and the Linvar model, both presented in
this chapter.VSat-based analysis of more complex models like the Psi-TFT model currently
only uses a small fraction (viz.VT ) of the intermediate parameters in the derivation of their
own parameter values. In future work, mapping of the full range of intermediate parameters
to selected transistor models could be elaborated.
In conclusion, theVSat method can contribute to modeling by providing a fully automated
way of deriving intermediate parameters which can be used a)to select feasible transistor
models for measured output characteristics, and b) to refinethese intermediate parameters
into parameters for more complex models.
92 Chapter 4. VSat Method
93
Chapter 5
Analysis of OFET-Based Logic Circuits
In this chapter, standard procedures used for characterizing OFET-based logic circuits will
be presented. First, commonly-used circuit concepts realizing OFET-based logic gates will
be discussed. Then, methods of assessing robustness and timing-related performance figures
of logic gates are detailed. Subsequently, existing tools for characterizing logic circuits are
reviewed. The discussion aims at identifying useful performance figures which quantify the
performance of certain OFET generations or circuit technologies as well as requirements of
circuit analysis on an integrated analysis framework.
5.1 Logic Circuits
Logic gates are the principal building blocks of logic circuits. They can be considered as com-
binations of “switching elements” used for computing operations from the Boolean algebra.
5.1.1 Basic Circuit Concepts
The most basic logic gate in a logic family is the inverter. InOFET-based logic circuits,
it is commonly represented in the form of a pull-down and a pull-up element switching the
inverter’s output to ground (GND) or to the supply voltage (VDD) via a low-resistance path.
Fig. 5.1 shows the schematics of commonly-used configurations of inverters.
In circuits operating with only one type of semiconductor (either n-type or p-type) for
both the pull-up and the pull-down element, the input of the inverter is connected to an input
or driving transistor. This transistor can shortcut the output toGND if the proper voltage
is applied. The pull-up element is then realized by aload transistorwhere the gate is either
connected to its source or to its drain. If the gate is connected to the source, a fixed gate-source
voltageVGS = 0 V results. This configuration will only work if the transistor is switched
94 Chapter 5. Analysis of OFET-Based Logic Circuits
Q
A
a)
Q
A
b)
Q
A
e)
QA
d)
QA
c)
MD
ML
VDD
MD
ML
VDD
MD
RL
VDD
MPU
MPD
VDD
MPU
MPD
VDD
Fig. 5.1: Basic configurations to implement an inverter: a) Load transistor (ML) in current-source load configuration, b) load transistor (ML) in diode load configuration, c) comple-mentary pull-up (MPU ) and pull-down transistors (MPD), d) complementary-like ambipolartransistors (MPU andMPD), and e) load resistor (RL) configuration.
on at a gate-source voltage of zero – a behavior referred to asnormally-onor depletion-
modein literature (e.g. [96, 97]). A normally-on transistor in this configuration yields an
approximately constant drain current as long as it operatesin the saturation region. Hence, the
configuration of a load transistor with the gate connected toits source is referred to ascurrent-
source load(CSL) configuration in this work following the definition of current-sourcing
load used by [98]. Fig. 5.2 shows the relationship between the output characteristics of the
transistors of a CSL-type inverter and itsvoltage transfer characteristic(VTC), which is the
plot of the output voltage vs. the input voltage. The numbered circles in both plots of the
figure denote corresponding operating points in the output characteristics and the VTC.
0
b)
loadtransistor
drivingtransistor
0
c)
output
input
a)
0
drai
n cu
rren
t (dr
ivin
g tr
ans.
)
2
1
(load trans.)drain current
output voltage
3
45
43
2
5
1
input voltage
outp
ut v
olta
ge
VDD VDD
VDD
Fig. 5.2: Relationship between output characteristics andVTC of a CSL-type inverter:a) schematic, b) output characteristics of driving and loadtransistor, and c) resulting voltagetransfer characteristics. The numbered points in b) and c) correspond.
5.1. Logic Circuits 95
If the gate of the load transistor is connected to the drain, afixed gate-drain voltage
VGD = 0 V results. This configuration does not rely on a normally-on transistor and yields
an output characteristic similar to a diode for the pull-up transistor. Therefore, this configura-
tion will be referred to asdiode load(DL) configuration in the following. OFET-based logic
gates in diode load configuration have been presented e.g. in[3].
Logic circuits in OFET technology usually employ load and input transistors of the same
semiconductor material. There are also reports on circuitsusing normally-off input and
normally-on load transistors fabricated in laboratory setups. Normally-offor enhancement-
modemeans that the transistor is switched off at a gate-source voltage of zero. For example,
Lee and colleagues [99] reported p-type inverters based on pentacene where the input transis-
tor operated with a negative threshold voltage and the load transistor with a positive threshold
voltage. The threshold voltage of the driving transistor had been shifted by a special treatment
of the insulator-semiconductor interface so that the device was switched off at a gate-source
voltage equal to zero. The combination of an enhancement-mode input and a depletion-mode
load transistor is a concept that was commonly used in the early days of MOS integrated
circuits and is referred to as enhancement-depletion (E/D)logic [97, 100].
The pull-up element can also be a transistor of complementary semiconductor type, i.e. n-
type charge carriers if the pull-down transistor is p-type and vice versa. This configuration is
usually employed in state-of-the-art logic circuits and isreferred to as CMOS (complementary
metal-oxide semiconductor1) logic [37, 101]. In CMOS-type inverters, both the gate of the
pull-up and the gate of the pull-down transistor are connected to the input. Examples of
organic complementary circuits can be found in [102, 103].
Alternatively, the transfer characteristics of ambipolarOFETs (see Section 3.2.8) can be
exploited to design inverters with CMOS-like voltage-transfer characteristics as shown in
Fig. 5.3. Unlike inverters with true normally-off complementary transistors, ambipolar in-
verters never reach the supply rails. This fact also complicates the implementation of more
complex logic gates like NANDs or NORs, because ambipolar transistors in series connec-
tions do not fully switch off.
Another option is to use a resistor as the pull-up element connecting the output to the
supply railVDD. Examples of circuits utilizing resistor loads have been presented e.g. in
[104].
1The expression MOS (metal oxide semiconductor) originatesfrom the early material structure of inversion-layer CMOS transistors consisting of a silicon dioxide (SiO2) dielectric sandwiched between a metal gate andthe semiconductor.
96 Chapter 5. Analysis of OFET-Based Logic Circuits
OutputInput
0
20
40
60
80
100
0 20 40 60 80 100ou
tput
vol
tage
input voltage
VDD
Fig. 5.3: Schematic and voltage transfer characteristic ofan ambipolar inverter.
5.1.2 Enhancements
The fact that most organic semiconductor materials exhibitweakly normally-on or weakly
normally-off behavior leads to poor performance of the input transistor as it can only be
switched off with difficulties. Unless the complementary-type circuit concept is used, the
logic levels are determined by the ratio between the channelresistance of the input transistor
at a given gate-source voltage and the resistance value of the load element. The switch-off be-
havior of the input transistor can be improved by applying a positive voltage at its gate. This
observation led to the realization oflevel shifterconcepts in OFET-based logic circuits [85].
In principle, the initial logic block is followed by an output stage which shifts the output volt-
age to more favorable voltage levels. For p-type semiconductors, output voltages around zero
are shifted to positive voltages. This technique has already been described in the early 1960s
for transistor-based logic gates [105] and has also frequently been used in logic circuits em-
ploying normally-on gallium-arsenide transistors under the name Buffered FET Logic (BFL)
[106]. With a level-shifter concept, however, an additional supply voltage is required and the
real estate and wiring complexity of circuits increases. Fig. 5.4 shows the schematic of an
inverter in level shifter configuration.
Other researchers switched from static to dynamic logic. Pull-up elements in ratioed logic
are implemented by the same types of transistors as pull-down elements and are statically
driven. If the transistors operate in current-source load configurations the sink current pro-
vided by the pull-up transistor is considerably lower than the drive current provided by the
pull-down transistor. An increased width-to-length ratioof the pull-up device boosts its sink
current but also its gate capacitance. The increased capacitance will limit the attainable circuit
speed. Use of a diode load configuration considerably reduces the parasitic capacitance at the
cost of a reduced noise margin (see Section 5.3.2) of the logic gates. In order to improve the
5.2. Circuit Characterization 97
A
Q
VSS
VDD
M1
M2 M4
M3
Fig. 5.4: Schematic of an inverter in level-shifter configuration.
performance of OFET-based logic circuits,dynamic circuit conceptshave been investigated.
Huitema et al. [107] reported on a logic circuit utilizing pentacene transistors and a 120-stage
shift-register with 2,160 transistors in a dynamic circuitconcept. The basic idea of a dynamic
circuit concept is to add a clock input to the logic gates. This clock is used for dividing the
operation of the gate into two phases: setup (also called precharge) and evaluation phase. In
the setup phase, the output of the gate is precharged to the logic high voltage regardless of the
input values. In the evaluation phase, the output goes to thelow level if the configuration of
the input signals forces it to do so, but will otherwise stay at the high level. Details about the
actual OFET-based implementation were not given in [107] but the concept of dynamic logic
is frequently used for implementing high-speed silicon-based logic circuits. Fig. 5.5 shows
the schematic of a NOR gate in dynamic logic. During the precharge phase, the input PRE is
used for charging the output to the voltage levelVDD while the inputs A and B stay at GND.
In the subsequent evaluation phase, the output may go to ground potential, depending on the
states of the inputs.
5.2 Circuit Characterization
Circuits are frequently implemented by combining prebuiltcells with different functionality in
order to implement the desired behavior [108]. Normally, chip manufacturers supply libraries
of the cells that can be used for developing the circuit with software for computer-aided circuit
design. These libraries contain specifications of the cellswhich describe their functional and
electrical behavior.
There exist tools for characterizing the electrical behavior of cells using circuit simulation.
These tools generate testbenches, carry out circuit simulations, and compile characterization
98 Chapter 5. Analysis of OFET-Based Logic Circuits
Q
B
PRE
A
VDD
Fig. 5.5: Schematic of a NOR gate in a dynamic logic configuration. The input PRE is usedfor precharging the output toVDD via the load transistor.
reports on circuit behavior.
In the domain of logic circuits, the following properties are characterized [108, 109]:
2 Robustness, i.e. valid logic levels and noise margin.
2 Timing, including rise/fall times, transition times, clocking requirements.
2 Driving capability, i.e. fan out characterization.
2 Input capacitance.
2 Characterization of power consumption.
These characteristics and especially the first two (logic levels/noise margin and timing) can
also be used for evaluating the performance of an OFET technology. Therefore, it is worth-
while to take a closer look at the mechanisms of the characterization process. The following
two sections will provide a discussion of methods characterization robustness (Section 5.3)
and timing (Section 5.4).
Robustness is discussed because most OFET-based logic circuits suffer from non-ideal
VTCs. The unity-gain method as the standard procedure for analyzing noise margins of logic
circuits (see Section 5.3.3) can only be applied with care. Timing characterization is discussed
because standard methods of deriving delay times and other timing data often assume well-
behaved clocking signals (with sharp slopes) which are not frequently used in low-cost organic
circuits. Therefore, alternate characterization methodshave to be investigated.
Other characteristics will not be detailed in the followingowing to the fact that standard
methods described in literature [37, 106, 110, 111] can readily be applied to organic logic
5.3. Characterization of Robustness 99
circuits. Moreover, these characteristics are more important for experienced chip designers
than for the analysis of the general performance potential of OFET technologies.
5.3 Characterization of Robustness
One important characteristic of logic circuits is theirrobustness. It defines the ability of a logic
circuit to safely detect and issue valid voltage levels for the distinct logic states in the presence
of adverse noise at the input signals. In a general way, noiseis defined as any deviation from
nominal voltages [112]. Sources for noise can e.g. be [113]:
2 Spurious signals or crosstalk which interfere with information-carrying circuit nodes.
2 Inherent fluctuations of device parameters owing to fabrication process or operating
point variations.
For OFET-based logic circuits, the contribution of device variations is more important
than spurious signals owing to the low packing density of organic logic circuits [114] and the
early stages in the fabrication technology. Several possibilities exist to derive information on
the robustness of logic circuits. A selection of these will be discussed in the following. First,
the method of equilibrium zones will be discussed as it helpsdefining valid voltage levels for
logic circuits in the presence of VTC variation. At its core,this method is only a qualitative
approach. Therefore, the concept of noise margin is presented as it introduces figures of merit
which can be measured. Then, the unity-gain method is detailed. It is the standard method for
state-of-the-art integrated circuits using CMOS devices but occasionally fails in assessing the
robustness of organic logic circuits. Therefore, the method of maximum squares is discussed
which is often used in non-CMOS circuits to analyze robustness. Finally, methods inspecting
certain gain values of the VTC are reviewed.
5.3.1 Method of Equilibrium Zones
Pierce [115] treated the problem of tolerance and robustness in 1963 by inspecting signal
regeneration in the presence of VTC variations. He introduced “equilibrium zones” in order
to assess the compatibility between different types of logic gates. In the following text, this
method will hence be referred to asmethod of equilibrium zonesin the following. To the
best knowledge of the author of this work, Pierce’s method isnot used in other literature on
noise-margin calculations.
The method of equilibrium zones starts by inspecting the VTCof a single-input non-
inverting buffer performing the Boolean identity operation Q=A, whereA is the input andQ
the output. The voltageVout at the outputQ of the non-inverting buffer is some functionf of
100 Chapter 5. Analysis of OFET-Based Logic Circuits
the input voltageVin at the inputA, i.e. Vout = f(Vin). A stable VTC has three equilibrium
points whereVin = Vout (see Fig. 5.6):
2 voltageVL for stable low level,
2 voltageVH for stable high level,
2 voltageVM for the metastable point between these two.
If identical buffers are arranged in a long chain of gates with the output of each gate
connected to the input of its successor then the following relationship between the inputVin,1
of the first gate and the outputVout,m of the last gate is given by:
Vin,1 < VM ⇒ Vout,m = VL,
Vin,1 = VM ⇒ Vout,m = VM ,
Vin,1 > VM ⇒ Vout,m = VH .
(5.1)
VM marks the boundary between valid voltage levels for the low and high states with
0 ≤ VL < VM < VH ≤ VDD, (5.2)
when assuming positive supply voltages (VDD > 0).
1A Q
0
Vin Vout
VDD
VDDVM VH
VL
VM
VH
VL
Vin
Vout
Fig. 5.6: VTC of a non-inverting buffer with equilibrium pointsVL, VM , andVH .
However, one single VTC for all gates is not realistic. Real gates will display slight
differences in their VTC shapes owing to parameter variations or switching noise. In these
cases, upper and lower bound VTCs can be defined and used for the preceding equilibrium
5.3. Characterization of Robustness 101
analyses. In the presence of upper and lower bounds, the analysis will yield equilibrium zones
instead of single equilibrium points (see Fig. 5.7). These equilibrium zones define regions
in which the final equilibrium points will lie. The points cannot be stated exactly owing to
the statistical nature in which the individual VTCs vary. More importantly, it is not known
in the region belonging to the metastable equilibrium points whether the output will increase
or decrease between two or more stages and eventually lead toa stable output high or low
voltage. Hence, the middle region is calledindeterminate zonein [115]. Valid logic levels are
required to avoid the indeterminate zone.
0
outp
ut v
olta
ge
input voltage
inde
term
inat
e
lower boundVTCupper bound
VTC
low
high
Fig. 5.7: Determination of equilibrium zones of non-inverting buffers using upper and lowerbound VTCs. The individual equilibrium points are marked bycircles.
The method of equilibrium zones can also be extended to inverters and more complex
gates. In the case of inverters, simply a pair of two gates is combined so to implement the
identity operation and getting plots in the form of Fig. 5.7.
Worst-case combinations of pairs of two inverters have to beconsidered in order to derive
the equilibrium zones. In spite of that, these zones are readily available when plotting the
upper and lower bound VTCs in a diagram together with their reflections about thex = y line
(see Fig. 5.8). Therefore, it is not necessary to calculate the VTC of the pair of inverters.
By use of the reflection, values on thex axis serve both as input of the first and output of
the second inverter while values on they axis serve both as output of the first and input of the
second inverter. At each intersection between a true and a reflected VTC, an equilibrium point
of the VTC of the respective pair of inverters is located. This is due to the fact that there, the
second inverter will transform its input voltage to a value equivalent to the input voltage of
the first inverter.
Once the equilibrium zones have been established their positions can be drawn in a dia-
102 Chapter 5. Analysis of OFET-Based Logic Circuits
0
outp
ut v
olta
ge, f
irst i
nver
ter
output voltage, second inverter
inpu
t vol
tage
, sec
ond
inve
rter
input voltage, first inverter
low
inde
term
inat
e
high
inverter
11
first secondinverter
Fig. 5.8: Determination of equilibrium zones for pairs of inverters by plotting true (solid lines)and reflected curves (broken lines) of the upper and lower bound VTCs. The individual equi-librium points are marked by circles. The inset shows the constellation of the two inverters.
gram to test the compatibility of gates with different equilibrium zones (see Fig. 5.9). If gates
are to be interconnected their indeterminate zones must notcoincide with either the high or
low equilibrium zones of their partners in order to yield regenerating signals.
? highlow
Driving Gate
0
0
low high?
Sensing Gate
VDD
VDD
Voltage
Voltage
Fig. 5.9: Compatibility diagram of two gates of different types. The boxes with the questionmarks denote the indeterminate zones.
5.3.2 Concept of Noise Margin
A drawback of the method of equilibrium zones is that, in its original form, it is only a qual-
itative tool. In order to compare the performance potentialof different circuit or device tech-
nologies by numbers, the concept of noise margin is helpful.
The noise margin can be calculated by defining four critical voltage levels in a VTC. An
5.3. Characterization of Robustness 103
inverter as the simplest form of logic gate detects and issues logic states according to the
following relationship between input voltageVin, output voltageVout, and the four critical
voltage levelsVIL,max, VIH,min, VOL,max, andVOH,min [116, 117]:
Vin ≤ VIL,max ⇒ Vout ≥ VOH,min,
Vin > VIH,min ⇒ Vout < VOL,max.(5.3)
Here,VIL,max (VIH,min) is the maximum (minimum) allowable voltage level for the logic
low (high) level at the input,VOH,min (VOL,max) is the minimum (maximum) allowable voltage
level for the logic high (low) level at the output. Moreover,positive voltages are assumed. The
relationships in (5.3) give rise to the voltage tolerance between inputs and outputs [116] as
NMH = VOH,min − VIH,min,
NML = VIL,max − VOL,max.(5.4)
The tolerance of a gate against variations of the input voltages is defined in terms of the noise
marginNML for the logic low level andNMH for the logic high level. In order to get both
NML > 0 andNMH > 0, the following relationships are required:
0 < VOL,max < VIL,max < VIH,min < VOH,min < VDD. (5.5)
The diagram in Fig. 5.10 can be used for visualizing the definitions in (5.4) and (5.5). In
the lower part of the figure, two gates are connected via a noisy path. It should be stressed that
noise sources can be spurious signals or variations in the transistors of the gates. The upper
part of the figure represents the graphical equivalence of (5.4) and (5.5)
There exists no general rule for the definition of the critical voltagesVIL,max, VIH,min,
VOL,max andVOH,min. Although the method of equilibrium zones can be used for defining
the critical voltages (see Fig. 5.11), this approach is not used in literature on noise margin
calculations. Instead, the unity gain method presented in Section 5.3.3 is often used. For
OFET-based logic circuits, however, it will sometimes predict negative noise margin for fully
functional logic gates.
A simple graphical test to determine whether a particular gate complies with given noise
margins [116] can be carried out. In the test, the VTCf(Vin) of the gate is drawn in the VTC
box and the shaded areas whereVout < VOH,min for all 0 < Vin < VIL,max andVout > VOL,max
for all VIH,min < Vin < VDD. A valid VTC does not enter these shaded areas (see Fig. 5.12).
104 Chapter 5. Analysis of OFET-Based Logic Circuits
1 1noise
VOL,max
gateM gateM + 1
VOUT
VDD
VIH,min
VIL,max
VOH,min
VIN
NMH
NML
Fig. 5.10: Definition of noise margins (adaption from [117]).
low
0
? high
VDD
VoltageVOL,max VOH,min
VIL,max VIH,min
Fig. 5.11: Definition of critical voltages using the method of equilibrium zones.
0
0
VIL,max
VOL,max
VOH,min
VDD
VIH,min VDD
Vin
f(Vin)
Vout
Fig. 5.12: Graphical VTC test for a robust inverter.
5.3. Characterization of Robustness 105
5.3.3 Unity Gain Method
A popular approach to determineVIL,max, VIH,min, VOL,max andVOH,min is theunity gain ap-
proach(see [116] and the references therein). Currently, it is themethod of choice in the deter-
mination of noise margins of CMOS gates. In this approach,VIL,max andVIH,min are given by
the -1 slope points in the VTC. The output voltages can be defined asVOH,min = f(VIL,max)
andVOL,max = f(VIH,min), see Fig. 5.13. This setup maximizes the sum of the two noise
margins [118]
NML + NMH = VIL,max − f(VIH,min) − VIH,min + f(VIL,max). (5.6)
The maximum value can be derived by finding the zero of the derivative ofNML+NMH with
respect toVIL,max andVIH,min. Zero is reached at the unity gain points where the relationsare
df(VIL,max)/dVIL,max = −1 anddf(VIH,min)/dVIH,min = −1. The reader should note that
negative noise margins can occur for eitherNML or NMH .
slope −1
slope −1
VIH,minVIL,max
Vout
Vin00
VDD
VOH,min
VOL,max
VDD
Fig. 5.13: Definition of input/output tolerance ranges withunity-gain method.
A drawback of the unity gain method is that definingVIL,max andVIH,min by the -1 slope
points is not a necessary condition when checking the validity of a VTC. Therefore, this
approach sometimes leads to negative noise margins for logic circuits because one of the -1
slope points does not exist. A negative value for a VTC would suggest that no regeneration of
input voltages to valid logic levels is possible. However, this is not true as can be seen from
the example in Fig. 5.14. For the VTC depicted in the figure, the unity gain method fails in
106 Chapter 5. Analysis of OFET-Based Logic Circuits
the calculation of the noise margin as only one -1 slope pointexists. Yet, the VTC possesses
three equilibrium points and hence, stable voltage levels for logic high and low exist.
slope −1
reflected VTC
inverter VTC
VDD
VOL,max
0 VIH,min
Vin
VDD
Vout
Fig. 5.14: Inverter VTC where the unity gain method fails butvalid logic levels exist.
Another problem of the unity gain method is that taking the critical valuesVIL,max, VIH,min,
VOL,max, andVOH,min from a single VTC is not reasonable as device variations can alter the
VTC shapes. As a solution to this problem, upper and lower bound VTCs can be derived and
worst-case points for the critical values can be selected from these.
5.3.4 Method of Maximum Squares
The problem of noise margins was treated in [119, 120] by inspecting an infinite chain of
inverters with identical VTCs. Noise can be modeled by voltage sources in series to the inputs
of the inverters in the chain. The worst-case noise condition occurs when noise sources are
present at the inputs of all gates with all low gate and high gate noise sources contributing in
the most deleterious way. This happens when driving the logic low inputs toward logic high
values and the logic high inputs toward logic low values.
In terms of noise analysis, the infinite chain of inverters together with their associated
noise sources can be substituted by a latch consisting of twocross-coupled inverters with
noise voltages in series to the inputs. In this configuration, only two inverters and two noise
sources have to be treated. The noise analysis is used for determining the noise levels which
force the latch to switch from a stored to the other logic state and consequently cause the
memory element to malfunction. The analysis can be carried out by inspecting the VTC of
the first inverter in the latch together with a reflection about the x = y line so that for the
5.3. Characterization of Robustness 107
second inverter in the latch, they axis serves as the input axis and thex axis as its output
axis. The same graphical representation was also used by Pierce [115] (see Section 5.3.1).
The latch retains the stored logic state as long as the two curves continue to intersect in three
points [121] even in the presence of deleterious noise, which will somehow shift the curves.
Fig. 5.15 shows a graphical representation of the extraction scheme. The latch in the left
part of the figure is used in the analysis and is equipped with noise sources. First/second
VIN /VOUT in the diagram are the input and output voltages of the first and second inverter.
In order to obtain the noise margin for the worst-case seriesvoltage, the maximum possible
square between the normal and reflected VTC is considered. The noise sources with maximum
allowable amplitudeVn,max are represented by the equally-sized sides of the maximum square
within the loop. Upon exertingVn,max at both noise sources in Fig. 5.15, the points of the
true and reflected VTCs at the corners of the maximum square coincide and there is only
one intersection point for both VTCs. For detrimental noisesources with amplitudes below
Vn,max, there still exist three intersection points between the two.
1
1
noise first
noise
source
source
inverter
secondinverter
00
outp
ut v
olta
ge, f
irst i
nver
ter
inpu
t vol
tage
, sec
ond
inve
rter
VDD
VDDinput voltage, first inverteroutput voltage, second inverter
Vn,max
Vn,max
Fig. 5.15: Graphical extraction of maximum-square noise margin.
The approach yields the maximum square noise margin and hence, equal noise margins
for logic low and logic high states. In real gates, attainable noise margins for the logic high
and logic low stare are normally not equal [116]. Therefore,it is sometimes more favorable to
consider the maximum possible product between the noise margin for the logic low and logic
high state. However, the calculation of the maximum square is far more feasible than the
calculation of the maximum product. The maximum square noise margin can be calculated
by rotating the true and reflected VTCs by 45° and then calculating the differences between
the two curves. These differences are equivalent to the diagonals of the squares between
108 Chapter 5. Analysis of OFET-Based Logic Circuits
diagonal points of the two VTCs. The calculation of the differences can even be carried out
in a circuit simulator as demonstrated by Seevinck and colleagues [122]. The procedure in
[122] consists of searching for the longest diagonal between the true and reflected VTC. Upon
rotating both curves by 45°, the original(x, y) coordinate system is translated into a(u, v)
coordinate system. In the latter coordinate system, thev values of the true and mirrored VTCs
can be subtracted in order to yield the diagonal. The magnitudes of the maximum positive
and maximum negative values correspond to the diagonal of the maximum square between
the two curves (see Fig. 5.16). [122] describes the true and reflected VTCs by the functions
y = F1(x) andy = F ′
2(x). F1 represents the true VTC andF ′
2 the reflected VTC of a second
gate with VTCF2. Owing to process variations or worst-case considerations, F1 andF2 may
differ. The transformation from(x, y) to (u, v) is
x =1√2u +
1√2v, (5.7)
y = − 1√2u +
1√2v, (5.8)
so thaty = F1(x) translates into
v = u +√
2F1
(
1√2u +
1√2v
)
(5.9)
andx = F2(y) into
v = −u +√
2F2
(
− 1√2u +
1√2v
)
. (5.10)
(5.9) and (5.10) can be used for calculatingv as an implicit function ofu. The maximum
value of the absolute difference between the twovs is equivalent to the maximum-square noise
margin times√
2. The solutions forv can be calculated in a circuit simulator using the setup
depicted in Fig. 5.17.
The noise margin as defined by the method of maximum squares isnot compatible with
the graphical test from Fig. 5.12. Unlike the unity gain method, it can easily cope with the
problem shown in Fig. 5.14. As long as there exists an openingin the loop between true and
reflected VTCs, a noise margin according to the method of maximum squares can be derived.
Like in the case of the unity gain method, calculating the maximum square from a single
VTC is not reasonable as device variations can alter the VTC shapes. Upper and lower bound
VTCs can be used for calculating worst-case maximum squares.
In work dealing with OFET-based noise margin calculations,the method of maximum
squares is preferably used (see [114, 123, 124]).
5.3. Characterization of Robustness 109
u
v
F1
F ′2
45
y
x
F1(u) − F2′(u)
Fig. 5.16: Extraction of maximum-square noise margin usinga coordinate system rotated by45° (adaption from [122]).
5.3.5 VTC Gain Considerations
In Section 5.3.1, the robustness of logic gates was treated by introducing the three equilibrium
pointsVL, VM , andVH for identity gates.VL andVH are stable equilibrium points whileVM
between them is metastable. Metastability is reached by a gain or slope of the VTC curve
at VM in excess of unity. For inverters, the VTC of a pair of inverters is inspected in order
to yield a logic identity function. If both inverters have identical VTCs,VM corresponds to
the intersection between the inverter VTC and the curveVout = Vin. The inverter gainGI
at Vin = VM is critical to the robustness of the gates. Hence, the expressioncritical gain is
used in this work forgcrit = GI(VM). In the case of inverters, the gain of the inverter pair
G(VM) = G2I(VM) so that|GI(VM)| > 1 is required. Conventionally,GI(Vin) ≤ 0 for all
sensible input voltages of an inverter so that a critical gain
gcrit < −1 (5.11)
is required for robust operation. Therefore, the critical gain can be used as a qualitative figure
which represents the robustness of an inverter. To the knowledge of the author of this work,
the concept of critical gain is not used elsewhere in literature on noise-margin calculations.
Instead, themaximum negative gaingmax = max |GI | is sometimes used in other publications
110 Chapter 5. Analysis of OFET-Based Logic Circuits
+
−
+
+
−
−
−
+
+
−
+
+
−
−
−
+
1
1
vout v1
vout v2
F1
F2
u
u
1√2v1
1√2u
√2vout + u
1√2v2
− 1√2u
√2vout − u
Fig. 5.17: Circuit to calculate maximum-square noise margin according to [122].
(e.g. [125]) for describing the robustness of a logic gate.
The difference between the critical gain and the maximum negative gain can be explained
by using the inverter gain and VTC plot in Fig. 5.18. The plotsshow typical simulation results
for an inverter in current-source configuration. Channel length and width of the driving tran-
sistor wereL = 5 µm, WD = 1500µm, and for the load transistorL = 5 µm, WL = 12 mm. In
the simulation, the driving transistor was mapped by a Linvar model while the load transistor
was mapped by a Level-1 model specifically tailored toward reproducing the zeroVGS curve.
More details about the simulations can be found in Section 6.3.1. The following values can
be extracted from the plot:VM ≈ -5.15 V, critical gaingcrit ≈ -2.1,gmax ≈ -8.3.
In the VTC,gcrit lies close to the negative unity gain whilegmax is located farther away.
This behavior is typical of OFET-based logic circuits without complementary devices for
the pull-up and pull-down path. As will be shown on p. 142, thecritical gain has a closer
relationship to the noise margin than the maximum negative gain.
5.3.6 Discussion of Characterization Methods
The method of equilibrium zones relies on knowledge about upper and lower bounds for the
VTC. This complicates application of the method because these bounds have to be found by
worst-case analysis, e.g. by time-consuming stochastic simulations or by knowledge about the
influences of the device parameters. This knowledge has to beestablished beforehand for the
logic family in use. On the other hand, the method of equilibrium zones yields a tangible way
of determining the compatibility of logic gates. This behavior is very important in the case of
ratioed logic which suffers e.g. from bias-induced parameter shifts. As another advantage, a
5.3. Characterization of Robustness 111
gain
VTCratio = 8
input
= o
utpu
t
−20
−15
−10
−5
0
−20 −15 −10 −5 0−9
−8
−7
−6
−5
−4
−3
−2
−1
0
outp
ut v
olta
ge [V
] −−
>
input voltage [V] −−>
VT
C g
ain
[] −
−>
Fig. 5.18: Plot of inverter VTC and inverter gain for a gate incurrent-source configuration:VM ≈ -5.15 V, critical gaingcrit ≈ -2.1,gmax ≈ -8.3.
sort of worst-case analysis is implemented by this method asthe lower and upper bounds mark
the expectable VTC conditions. Noise introduced by parameter variation and subsequent VTC
shift is explicitly treated and therefore, a precise analysis of static noise margins is possible.
The unity gain method is mainly used in the analysis of modernCMOS circuits. Noise
margins can easily be extracted from a measured or simulatedVTC by considering the points
where the derivative ofdVout/dVin = −1. However, there exist conclusions ([116]) that only
techniques based on embedding some area within the true and reflected VTCs give reliable
noise margin values for a broad range of possible VTCs. Theseresults are consistent with
findings in this work (cf. p. 142). For non-CMOS circuits, noise-margin considerations based
on the unity gain method easily yield negative noise marginsalthough the maximum-square
method predicts the existence of positive noise margins.
With the method of maximum squares, the maximum square noisemargin can easily be
obtained by simulation (see Section 5.3.1). A drawback of the method is that variations in
fabrication and environmental conditions are modeled withconstant noise sources in the form
of series voltages. These variations lead nevertheless to nonlinear VTC changes. For example,
the noise margins for logic high and logic low states are affected differently as has been shown
in [126]. This problem could be solved by inspecting lower-bound and upper-bound VTCs in
a similar way as in the method of equilibrium zones.
Evaluation of the critical gain of an inverter VTC is a quick method of checking the ro-
bustness of the gate. The calculation of the maximum negative gain on the other hand is
more frequently used in literature on noise-margin calculations. It is more useful in the as-
112 Chapter 5. Analysis of OFET-Based Logic Circuits
sessment of CMOS-type gates with well-behaved VTCs. Both methods (critical gain and
maximum negative gain) suffer from calculation inaccuracies in the derivation of the gain
from the VTCs.
Generally, it is questionable whether voltage sources are sufficient to map the noise con-
tributions of parameter variations on VTC shapes in the derivation of noise margins. Further
investigation seems to be in order. For example,VT or λ shifts are more critical for the low
levels of CSL-type inverters (see Fig. 5.2). The resulting behavior will not be correctly repro-
duced by shifting the VTC with voltage sources. Instead, worst-case considerations of VTCs
need to be used for defining valid noise margins.
5.4 Timing Characterization
Timing characterization shows the attainable speed of a logic cell. Numerous timing figures
have been defined as meaningful performance figures: rise, fall, and delay times. They mea-
sure the response of a gate to a voltage pulse (e.g. [113]). The rise (fall) time is typically
measured from 10% to 90% (90% to 10%) of the difference between the logic low (high) and
logic high (low) state [101]. There also exist definitions using 20% and 80% thresholds [106].
The delay timetD represents the time interval between input and output levels being half way
between logic low and logic high states.
The delay time is an important timing figure in systems with a large number of logic gates
in series where the net delay between the input and the outputof the system is large.
A step pulse is typically used for calculating the timing behavior of logic circuits. Analyti-
cal expressions have been derived to predict these times. Popular methods rely on simplifying
assumptions like constant capacitances or negligible influence of feedback effects in the cir-
cuits [127]. Moreover, the response time of a gate is normally longer than the transition time of
a step pulse at its input [128]. Hence, using step pulses overestimates the gate delay [129] and
more sophisticated analysis techniques have been developed to deal with the non-idealities of
logic gates (see e.g. [113, 128, 129, 130, 131, 132]).
Alternate definitions of relevant transition times can be found e.g. in [133], where the
input signal transitions are not restricted to unrealistically ideal steps but instead resort to
ramp signals with finite slopes. Fig. 5.19 details the definitions of the transition times, which
are derived as follows:
2 tf is thefall time indicating the time interval to decreaseVout from its 90% to its 10%
point. This time is also referred to asslew[134].
2 tr is therise timeindicating the time interval to increaseVout from its 10% to its 90%
point.
5.4. Timing Characterization 113
2 tdf is thehigh–to–low delay timeindicating the difference between the 50% point of the
input rising transition and the 50% point of the output transition from high to low.
2 tdr is thelow–to-high delay timeindicating the difference between the 50% point of the
input falling transition and the 50% point of the output transition from low to high.
VOH
VOLt
t
VOH
VOL
90%
10%
tdrtdf
tf tr
50%
50%
Vin(t)
Vout(t)
Fig. 5.19: Definition of switching times based on an input signal with ramp-like high and lowtransition slopes.
In the case of unbalanced rise and fall times, anaverage propagation delayin the form of
tP = 12(tPHL + tPLH) can be defined. Alternatively, thepair delaytPD represents the delay
of a pair of identical gates. The pair delay is equivalent to the time delay between the time
points where the input of the first gate and the output of the second gate reach 50% of their
voltage swing [135].
The various response times presented in the preceding paragraphs always have to be re-
lated to the capacitive load of the gate under characterization, i.e. the fan-out. Thefan-out
(FO) is a value counting the number of identical gates drivenby a specified output [101].
An increase in fan-out leads to additional capacitance at the output of a gate. So, reports on
response times always need to specify the output capacitance for which the times have been
obtained. Similarly, afan-in (FI) can be defined as the number of inputs a gate possesses
114 Chapter 5. Analysis of OFET-Based Logic Circuits
[101]. For example, a 4-input NOR gate has a fan-in of four. The fan-in can also be important
for the response times. This is due to the fact that input transistors influence the charging and
discharging of the output node by providing additional capacitance and/or leakage currents.
Schrom [125] points out that the relation between the response times and the average fan-
in/fan-out is difficult to derive. Numerous models have therefore been developed to predict
this relationship [125, 134].
For numerical analyses in simulations, valid voltage levels for high and low voltages are
needed in order to calculate the measurement points. In CMOSconcepts, there is no need to
derive logic levels as usuallyVDD/10, VDD/2, andVDD can be assumed. Conversely, the real
values of both logic levels in ratioed logic depend on devicegeometries and parameter varia-
tions. Therefore, the voltage levels for these logic levelsneed to be established beforehand. A
practical approach in analysis, simulation, and measurement is to use ring oscillator circuits to
produce reasonable waveforms (e.g. [98, 125, 136]). Aring oscillator is a chain of inverting
gates with an odd number of stages. The simplest form of inverting gates can be inverters (see
Fig. 5.20) but other gates like NAND or NOR are also suitable.The output of each gate is
connected to the input of its successor. The output of the last gate is fed back to the input of
the first gate. This configuration leads to an oscillation with a frequency off ≈ 1/(2ntD)
wheren is the number of stages andtD is the delay per stage. The advantage of this approach
is that it yields the attainable voltage levels and transition times under realistic conditions. On
the other hand,n has to be chosen to be sufficiently large in order to allow the output voltages
of the gates to settle in response to rising and falling edges. But a large value forn also leads
to a long period time1/f which has to be simulated.
1 1 1
Fig. 5.20: Schematic of a ring oscillator composed of inverters.
Generally, the definitions of the transit times need to be used carefully because the results
depend on the input waveform and output load [125]. Due to different rise and fall times, even
negative delay times may occur [108]. In order to model the influence of input waveform and
output loading, logic cells are usually characterized by tables or equations that relate delay
time and output slew as a function of load capacitance and input slew. By using tables or
equations, timing models for logic simulation and circuit synthesis are possible. In this work,
performance figures are only used for comparing different device generations or logic families.
Consequently, these advanced techniques are considered tobe beyond the scope of this work.
The interested reader is referred e.g. to [137] and the references therein for a more detailed
discussion of the topic.
5.5. Automation of Circuit Characterization 115
5.5 Automation of Circuit Characterization
To carry out circuit characterization in an efficient way, a high degree of automation is re-
quired. Therefore, numerous software packages exist to aidthe users in the process of circuit
analysis. In the field of OFET-based semiconductor technologies, the analysis results assist
in the optimization of devices. Design automation tools canbe used for determining various
electrical characteristics of circuits. These tools are referred to ascircuit characterization
tools and can be broadly separated into characterization tools for logic circuits and general
characterization tools.
5.5.1 Tools for Characterization of Logic Circuits
Circuit characterization is frequently used for deriving various electrical characteristics of
logic circuits like timing, power consumption, or input capacitances in a form usable by digital
simulation and cell-based circuit synthesis. The latter transforms an abstract description of a
system into a real implementation by generating an integrated circuit. Logiccells like logic
gates or flip-flops are used as the building blocks of the system. The synthesis algorithms need
descriptions of these cells in order to take performance limits into account when numerous
inputs are connected to one single output, etc. Hence, issues like the determination of input
capacitance or timing behavior are emphasized in the characterization of logic circuits. The
focus in this domain is to provide simple models that can be used in calculations during the
synthesis or simulation process.
Characterization tools automatically characterize cells, i.e. provide model parameters use-
ful for logic synthesis, logic simulation, timing and poweroptimization, or create data books
for designers. SPICE simulations are typically used for measuring and extracting the electri-
cal parameters of logic cells. These parameters are calculated at individual process, voltage,
and temperature corners. A cell under characterization is embedded into a test circuit, where
it is evaluated with reasonable conditions.
A non-exhaustive list of commercial tools includes Z circuit ZChar [138], LibTech LibChar
[139], Synopsys NanoChar [140], Simucad AccuCell [141], orMagma SiliconSmart [142].
During the activities in this work, the author could only experimentally evaluate the open-
source characterization tool Autochar [111]. The other packages were evaluated using the
respective operation manuals, user reports, or conferencepresentations. Autochar is written
in the popular scripting language Perl and is used for circuit characterization with Synopsys
Star-Hspice or Silvaco SmartSPICE. The tool automates the generation of test circuits useful
in the extraction of load delay, input capacitance, setup and hold times for D-type flip-flops
(DFFs) as well as clock enable and clock-to-Q time for clocked DFFs (Q=output of the flip-
flop). Autochar is specifically tailored toward the characterization of CMOS-type circuits.
116 Chapter 5. Analysis of OFET-Based Logic Circuits
This property is reflected by the fact that e.g. delay times are measured between the fixed
thresholds of 10 and 90% of the supply voltageVDD. In order to be useful in timing analysis
for OFET-based circuits, Autochar would have to adapt to varying voltage ranges for logic
levels. Moreover, the package does not provide the determination of static noise margins.
The analysis flow is managed by a control file in Perl notation.References to netlists
and model sets are stored within this file as well as a specification of the desired analyses
and characterization conditions. The tool reads the control file and generates the relevant test
circuit according to the specifications of the input vectors, waveform slopes, and gate loads.
Then, the tool calls the simulator and retrieves all required information from the simulation
results. The data are interpreted and a characterization report is generated.
In contrast to commercial tools, Autochar does not provide sophisticated automation of
cell characterization. The package does not automaticallyanalyze the structure of cells un-
der characterization in order to derive their logic functionality and required testbenches. It
is the responsibility of the user to define functionality andmode of input excitement. More-
over, there exists no graphical user interface. Instead, Perl-style configuration files have to be
written. On the other hand, Autochar is open source software. Users can readily extend the
functionality of the package. However, the last official release of the software dates back to
the year 2000. Other tools like AccuCell are more flexible when dealing with timing thresh-
olds but do neither include analyses for static noise margins (see Section 5.3.2) nor graphical
user interfaces.
In general, characterization software for logic circuits already implements standard analy-
ses necessary in the treatment of logic circuits (power consumption, circuit speed, etc.). Some
tools require only little work for the configuration of the analyses. These tools try to derive the
logic functionality by inspecting the structure of the cells under consideration. Yet, commer-
cial cell characterization packages are expensive tools where pricing starts at $55,000 [143].
Moreover, the tools mostly implement features not needed inthe analysis of OFET-based
circuits with considerably lower structural complexity than the usual logic cells in CMOS li-
braries. On the other hand, simple analyses like the automatic determination of frequencies of
ring oscillators or static noise margins are missing.
5.5.2 General Characterization Tools
The tools mentioned in the previous section focus on the treatment of logic circuits. In this
section, tools are discussed which characterize circuits in a general way. Normally, these
tools can also be used for automatically sizing the devices within a circuit, i.e. the lengths and
widths of the transistors or the resistance values of the resistors, etc., by use of optimization
strategies. There exist different tools with distinct applications, which also employ specific
5.5. Automation of Circuit Characterization 117
optimization schemes. Automatic sizing is less important for low-complexity circuits like
simple logic gates. These circuits can also be sized manually. Tools for circuit sizing get
important when circuits of higher complexities need to be implemented or optimized. In spite
of that, they provide interesting features for the analysisof OFET-based circuits like automatic
testbench generation or generic simulator interfaces. Hence, their evaluation is worthwhile.
In the following, a selection of tools with specific featuresis presented.
The schematic editor STAR [144] focuses on reusing designs in analog circuit design. The
idea is to add comments to circuit schematics in order to carry out predefined functions from
a library. An execution engine then processes these comments in order to generate necessary
computation routines. The goal of STAR is to create a flexiblelibrary which can be extended
with user-specified functions. The prototype tool is composed of four layers: a schematic
capture, a comment parser, an analysis layer, and a data processing layer at the bottom. The
system is implemented by a mixture of code in Tcl/Tk, Perl, and C. The central component
in STAR is the circuit schematic from which all further action is derived by inspecting the
comments embedded in it.
ASF (Analog Synthesis Framework) [145] employs simulationmethods used by designers
to validate manual circuit designs during a circuit generation process. ASF incorporates mod-
ular, reusable, and user-configurable testbenches, which are called evaluators by the authors
of the package. The focus of ASF is to provide an easy-to-use and general tool where the
user can create any topology for any desired manufacturing process. The concept implements
an open framework for measuring arbitrary circuit characteristics with minimal effort. A ma-
jor goal of ASF is to feature a robust optimization and searchheuristic that operates within
reasonable run-time. In order to achieve this goal, a stochastic search engine is employed for
solution finding. A special feature of ASF is to encapsulate simulators within an abstract layer
so that any simulator with an appropriate interface can be used with the package. This concept
is calledsimulator encapsulation.
A commercial sizing tool is NeoCircuit from Cadence [146]. It automates circuit sizing
and uses the designer’s simulator, testbenches, and transistor models to automatically evaluate
circuit solutions generated by its solver. All explored sizing candidates are preserved in a
database for further analysis. A user report on NeoCircuit is given in [147]. The tool features
a text console used for controlling the flow of the program as well as a graphical user interface
with almost the same functionality. For post-processing purposes, data can be exchanged with
the engineering software Matlab and its open-source clone Octave.
Conn and colleagues [148] report a sizing system called JiffyTune. It utilizes a circuit
simulator called SPECS and an optimization engine called LANCELOT. JiffyTune requires
the specification of a circuit schematic, input signals, a list of “tunable” transistors, with initial
widths, and a set of circuit performance requirements. The package determines the optimal
118 Chapter 5. Analysis of OFET-Based Logic Circuits
assignment of transistor widths to achieve the requirements. SPECS is a circuit simulator
which uses simplified device models and event-driven simulation to decrease simulation time.
LANCELOT, the optimization engine, repeatedly calls the simulator with different settings
for the transistor sizes in order to model the performance ofthe circuit. The authors in [148]
note that JiffyTune is driven by a textual control file and requires knowledgeable users. Nev-
ertheless, it provides an interface to the Cadence design system.
The above-mentioned packages focus on sizing transistors for a particular design, i.e. de-
termining their optimal width and length. A more general characterization tool is the analysis
environment Decida, which was released as open-source in 2002 by Agere [149]. The envi-
ronment allows a circuit designer to customize the set of analyses, to control and integrate
design tools, and to provide analysis and plotting capabilities [150]. Decida is implemented
using the scripting language Tcl/Tk and can be extended veryflexibly. Like JiffyTune, it
resorts to the optimization engine LANCELOT in order to optimize circuits.
The characterization tools discussed in this section focuson the characterization and/or
optimization of individual circuits. Therefore, their view and user concept centers on a par-
ticular design (e.g. operational amplifier, etc.) in the form of a netlist or schematic. Some
tools do not automatically generate testbenches. Instead,the users compose their own test-
benches and define which parameters to optimize. Other toolsalready provide pre-generated
testbenches or allow the users to compile reusable libraries of testbenches.
The OFET-based approach discussed in this work focuses on bringing together models
and circuits and carrying out analyses on the combination ofboth. The circuit is not central
to the analysis but the results obtained from combining it with the transistor models. This
approach is more similar to batch-mode circuit characterization of logic circuits. To carry out
this kind of analysis with the above-mentioned general analysis tools, an additional step of
compiling a tractable schematic description would be necessary. Moreover, the existing tools
do not provide special means to generate and manage device models or heterogeneous sets of
data (schematics, models, data vectors, etc.).
5.5.3 Discussion
Characterization tools come in two flavors: specialized characterization tools for logic circuits
and general circuit analyzers. The former focus on creatingparameter sets useful in digital
simulation and synthesis. They work on libraries of gates with given models. Variations of cir-
cuit or device parameters are not considered by these tools but have to be provided by the users
in the form of special models. General analysis tools on the other hand focus on the flexible
manipulation of circuit parameters. Their primary building blocks are netlists or schemat-
ics. These tools do not carry out batches of different analyses with different testbenches to
5.6. Chapter Summary 119
generate.
Individual tools manage design databases into which all generated data can be included.
Yet, since the tools do not completely cover the analysis of OFET-based circuits and transis-
tors, e.g. modeling data are not included in the database.
From the user’s point of view, a combination of the cell characterization scheme (auto-
matic testbench generation for different combinations of models and circuits) with the flex-
ibility of general circuit analyzers (parameter variationor performance optimization) would
considerably improve efficiency of the tools. This would also reduce the work in planning and
maintaining the computer experiments because the testbenches are automatically generated by
the computer.
For the human analysts who employ circuit characterization, implementation of the fol-
lowing features by characterization tools is desirable:
2 Circuit Management– Alternative circuit designs need to be managed by the charac-
terization tool. This allows the users to select benchmark circuits from different circuit
technologies (e.g. logic gates with load transistors in current-source configuration, etc.)
without the need to compile these libraries themselves. Thelibraries should also be
reusable in later analyses.
2 Reusable Analysis Procedures– The procedures for deriving the electrical performance
of circuits need to be reusable with different sets of models, model parameters, and cir-
cuits to use. Even the operating conditions like supply voltage or ambient temperature
need to be adjustable.
2 Documentation of Analysis Procedures– In order to facilitate documentation and back-
tracking of unexpected analysis results, the analysis procedures need to be documented.
2 Flexible Compilation of Analysis Procedures– General analysis procedures should be
easy to compile. In the analysis of OFET-based logic circuits, standard procedures for
deriving meaningful performance figures still need to be established. Therefore, the
analysis tools must be flexible enough to allow the users to reconfigure the analysis
procedures.
5.6 Chapter Summary
In this chapter, procedures for characterizing OFET-basedlogic circuits were discussed. The
following items summarize the discussion results:
2 Circuit analysis with emphasis on organic electronics is still in the early stages. Only
few publications analyze the impact of OFET parameters on circuit performance.
120 Chapter 5. Analysis of OFET-Based Logic Circuits
2 Characterization procedures established for traditionalsemiconductor technologies can
also be used for analyzing the performance of OFET-based logic circuits. These proce-
dures include e.g. static noise margin determination, delay measurement, etc. However,
the methods have to be applied with care because they often predict false results when
dealing with OFET-based circuits. For example, the unity gain method of deriving noise
margins occasionally predicts negative noise margins for functional circuits. Besides,
deriving delay times using step pulses does not reflect the clock generation schemes in
organic logic circuits (where ring oscillators provide clock signals).
2 Existing tools for circuit characterization are not adapted to the special needs of OFET
technologies. Integration of transistor modeling is missing, or basic analyses like the
calculation of maximum-square noise margin are not included. Moreover, the tools are
specifically designed for skilled users of simulators like SPICE and difficult to work
with for the occasional and non-expert user. Often, flexiblecombinations of different
analysis steps into more complex analyses is not possible orrequires special program-
ming knowledge.
Chapter 6 will detail an analysis concept in which OFET-based logic circuits can be an-
alyzed. The concept provides a flexible interface which allows non-expert users to compile
powerful analysis scripts in a graphical way. OFET modelingand data management are also
included.
121
Chapter 6
Analysis Concept
This chapter presents an analysis concept that automates modeling of organic transistors and
characterization of OFET-based logic circuits. The basic idea is to integrate the various soft-
ware tools needed during the analysis into one single platform. The collaboration between
these tools is automated and the required data are managed ina coherent fashion. This ap-
proach allows the device analyst to concentrate on improving the devices and circuits rather
than transferring data between different tools and manipulating result vectors in order to ex-
tract meaningful performance figures. The novelty of the concept is the combination of all
of these tasks in a single environment. Automation of the analysis is reached by a graphical
scripting concept, which allows non-expert users to compose new or alter existing analysis
procedures. With this framework, routine work is delegatedto the computer.
The chapter is organized in the following way. First, the typical analysis flow is exam-
ined in order to identify drawbacks of existing solutions. Subsequently, the novel concept
is detailed. Finally, circuit analyses using an experimental implementation of the analysis
framework are demonstrated.
6.1 Typical Analysis Flow
The optimization of OFET devices and circuits based on circuit simulation is an iterative
process. In practical research work, the process typicallyconsists of the following steps (cf.
Fig. 1.1):
1. Transistor models are extracted from the measured curves.
2. Netlists are generated. These contain test circuit, devices under test, and the necessary
models. The user has to compile the respective circuits intoa netlist and to include the
model descriptions.
122 Chapter 6. Analysis Concept
3. The circuit simulator is executed, which interprets the netlists, simulates the circuits,
and reports calculated results.
4. The analysts (researchers or computer programs) interpret the results and generate data
sheets from the information. They ask questions like the following:
2 What is the performance of a given device generation in logiccircuits?
2 Which device and circuit parameters define performance (e.g. robustness against
interfering noise, circuit speed, power consumption, etc.)?
2 Where have the parameters to be pushed to in order to increasethe circuit perfor-
mance?
Answering these questions involves variation of the circuit and model parameters so
that different device generations and parameter sets can betaken into account.
Existing software tools can cover the individual aspects ofthe process. The analysis cycle
is complicated by manually coordinating the steps due to thefollowing reasons:
2 Data have to be transferred between the tools called in the individual operations. Model
sets need to be included into the netlists used in the simulations or circuits have to be
inserted into the testbenches, etc. These processes are time-consuming and error prone.
2 Input data and analysis results have to be preserved in a database in order to document
the analysis process, to record the improvements of a fabrication process, or to support
replay of the analyses. Possibly, many iterations of the analysis are needed so that
preservation of data can quickly get out of hand.
2 The users need to understand numerous tools and data formats. After longer periods of
not working with the analysis tools, this knowledge often has to be reactivated.
The author of this thesis concludes from practical experience that existing tools will fail
to be used in the analysis of OFET-based devices and circuitsas long as the following issues
are not resolved:
1. A single software environment is needed. It must be easy touse. The users, who
normally do not work in the domain of circuit simulation, arenot interested in learning
to use the individual tools. Instead, they want to focus on getting their results quickly
and in a highly automated way. Therefore, they prefer graphical user interfaces and easy
access to all relevant data and functions.
6.1. Typical Analysis Flow 123
2. The environment must integrate modeling of the transistor devices in an easy-to-use
fashion. Contrary to more traditional semiconductor technologies, vendor-supplied
transistor models do currently not exist in organic electronics. For the user of OFETs,
modeling is therefore most often the starting point of the analysis cycle.
3. The environment must provide automatic generation of test circuits. These test circuits
include e.g. setups for measuring performance figures like noise margin or circuit speed.
4. The environment must provide preconfigured analysis procedures and libraries of pop-
ular logic gates. For the users, it is important to have template setups and gates which
they can reuse and adapt to their special requirements. Otherwise, the users would have
to create the necessary circuits and analysis procedures manually.
5. In the generation of test circuits, transistor models must be easy to replace. There exist
many variations of OFETs (alternate semiconductor / dielectric / electrode materials,
top-gate or bottom-gate topology, etc.) and hence many model types. A generic analysis
tool must therefore manage different model types in all of its analyses. Here, model
management is understood to include the ability to conveniently replace models in test
circuits and analysis setups.
6. The analysis procedures must be easy to adapt to new requirements or to include novel
extraction schemes. Users prefer generic analysis procedures which they can manipu-
late and flexibly extend.
7. In the course of an analysis, model parameters or transistor geometries may have to be
varied. A framework must therefore provide mechanisms to dynamically vary model
and device parameters.
8. The environment must automatically collaborate with a variety of circuit simulators,
i.e. create simulation-ready netlists for the test circuit, execute the target simulators, or
extract the simulation results. This property is highly desirable because many different
simulation tools are available.
Existing tools easily cover individual aspects of the abovelist. But missing is an inte-
gration framework in which all of these tasks are handled in acoherent fashion. This work
provides the concept for such a framework, which automates the analysis of novel OFET
devices by use of a generic, coherent, and flexible analysis system.
124 Chapter 6. Analysis Concept
6.2 Novel Analysis Concept
The discussion in the previous section showed that an analysis flow constructed from tradi-
tional EDA tools suffers from numerous drawbacks. Therefore, a novel analysis concept has
been developed in this work. The concept describes how OFET-related data are stored and
analyses of device performance are carried out. The noveltylies in the unified and object-
oriented organization of data, analysis scripts, and analysis reports.
The concept consists of an interactive modeling and simulation environment, and defines
a set of central ideas:
2 Data Management: All relevant data items used in the analyses are stored in ahier-
archical data treesimilar to a directory structure on a computer disk. Data items can
be measurement data, model sets, circuit descriptions, or analysis scripts. Each data
item in the tree can also have a documentation text and user-defined properties. The
hierarchical data tree serves as the analysis database and stores analysis procedures and
libraries of popular logic gates as well as user-supplied measurement data.
2 Modeling System: The modeling of devices is integrated intothe framework. Model
sets can be created and altered within the software environment. A standardized mod-
eling interfaceallows the users to add novelmodel extractors. This modeling interface
defines how the modeling tools are configured and used.
2 Analysis Control: Users employ analysis scripts to automate the analysis flow. Each
script consists of a sequence of individual analysis steps which can be defined and edited
using a graphical user interface. Parameters of circuits and models can be altered within
the scripting system. Batch-mode analyses with automatic generation and simulation of
different testbenches are possible. Astandardized execution interfaceallows the users
to include novel analysis steps. The execution interface defines the way how an analysis
step is graphically configured and executed.
2 Simulator encapsulation: Circuit simulators are integrated into the analysis concept by
use ofstandardized simulator interfaces. The interfaces cover netlist generation, sim-
ulator control, and result propagation. This technique is known assimulator encapsu-
lation [145] and has successfully been used in the optimization of circuits. Simulator
encapsulation is highly desirable as only the simulator interface has to be adapted in
order to link a novel circuit simulator to the analysis framework.
The following paragraphs provide a more detailed discussion of the concept.
6.2. Novel Analysis Concept 125
6.2.1 Data Management
Efficient data management provides a sensible and easy-to-use way of managing heteroge-
neous sets of data. Efficiency can be reached by using a unifieddata-management scheme,
i.e. all relevant data objects are stored within a coherent data repository. The analysis cycle
for OFET-based circuits typically includes objects of different types:
1. measurement data,
2. parameter sets for transistor models,
3. logic gates, i.e. circuits,
4. analysis scripts.
In the concept presented here, data are organized by storingall objects in a single hierar-
chical structure. This structure can be accessed by the userin the form of a hierarchicaldata
tree. Hierarchical in this context means that objects can contain other objects. Drawbacks of a
hierarchical data tree are that more efficient data management schemes which are utilized by
database management systems (DBMS) are not available, memory consumption is increased,
and searching the whole tree can take a long time. On the otherhand, the advantage of the
hierarchical tree is that data can easily be structured, i.e. grouped, according to the desires of
the users. This increases flexibility and ease of use becausethe users can organize and handle
the data according to their needs.
In order to facilitate use of the hierarchical data tree, it can e.g. be represented in a graph-
ical way similar to the files of a computer disk by the file browsers of popular operating
systems. With a graphical user interface, non-expert usersdo not need to learn the commands
of a system which works with batch-mode command scripts or aninteractive command line.
Moreover, most computer users are accustomed to the conceptof a graphical file browser. The
principal idea of the concept is to organize data in a hierarchical tree of different items so to
cover all important data-management aspects of the analysis cycle.
Fig. 6.1 shows an example of a hierarchical data tree. Data types defined by the concept
are:
2 analysis (icon )
An object of this type represents ananalysis procedure, which defines the individual
steps in the characterization of circuits and models. In theanalysis concept, analysis
procedures are represented by tree-form scripts implementing execution trees. Details
about tree-form scripts and execution trees are provided inSection 6.2.3.
126 Chapter 6. Analysis Concept
Fig. 6.1: Example of a hierarchical data tree.
2 circuit (icon )
An object of this type represents acircuit useful for testbench generation. The object
holds information on the structure and connectivity of the circuit. The structure defines
which devices are present in the circuit and how they are connected with each other.
Netlists or schematics are possible. The connectivity defines which terminals of a circuit
to the outer world are present in the circuit, their types (input, output, bidirectional, or
supply node), which parameters exist for the circuit (e.g. the dimensions of the critical
devices), and their default values.
6.2. Novel Analysis Concept 127
2 container (icon )
This object type enables the introduction of data hierarchyby acting as a folder into
which other objects can be grouped. It is comparable to a directory in a file system of a
computer.
2 model (icon )
An object of the type “model” is used for representing a transistor model in the analysis
system. The simplest form of a model is a property list in which the individual entries
denote the parameters of the model. The model can be bound to amodel extractor,
which is used for deriving the model parameters.
2 wavevar (icon )
“wavevar” objects contain waveform data like measured current curves, x-axis values
in simulations or measurements, etc. This kind of object is generated when a data file is
imported or simulation results are stored in the data tree.
2 wavefile (icon )
A wavefile object is created when a data file containing measurement or simulation
results is imported into the data tree. The wavefile object represents the imported data
file and contains either wavevars or again wavefiles.
In order to provide more-detailed descriptions of objects,meta data can be assigned to
objects.Meta dataare a form of additional data describing the object [151] they belong to.
In the concept detailed in this chapter, meta data are used for providing classification and
documentation of objects. The following forms of meta data are used:
2 A documentation textwhich is attached to an object so to document its use or method
of creation in a form easily readable by humans.
2 Property listsprovide tables with pairs of names and values where additional object-
related data can be stored in a more formal manner than in a documentation text. This
allows computer routines to directly access these tables. Therefore, search queries like
“list all objects with the propertylevel > 1” get possible. The property list can e.g.
contain the creation date of the object, the file from which the object was created, or in
the case of transistors, the width and length of the device, etc.
Using a combination of documentation text and property lists allows a thorough descrip-
tion in a form easily readable by humans and machines. Fig. 6.2 sketches the relationship
between objects and associated data.
128 Chapter 6. Analysis Concept
object
(text, ...)
documentation
valueprop name
properties
type−specific data
e.g. waveform, netlist, etc.
Fig. 6.2: Data association for objects: documentation, properties, type-specific data (wave-forms, netlists, etc.).
6.2.2 Modeling System
In the analysis framework, models are represented by objects of type “model”. These objects
usemodel extractorsfor extracting model parameters from measured curves. In this work, a
model extractor is regarded as a software module used for configuring a model object. The
model extractor can be a piece of software entirely contained within the framework core or
an interface to an external program which carries out the actual parameter extraction. The
generator provides a dialog in which the extraction processis set up, carried out, and possibly
repeated later on with different settings.
Standardized Modeling Interface
Model extractors are used for transforming measured devicecharacteristics into parameter
sets for a special model. They are realized in the analysis framework by use of dynamically
loadable modules. Each module provides a standardized function to create a graphical dialog
used for creating or modifying a model set. The details of themechanisms are specific to the
actual implementation of the analysis framework and will not be discussed here.
6.2.3 Analysis Control
Automatic device and circuit analysis is an important aspect of the analysis cycle. The task
is handled by analysis control. In this work, the termanalysis controlrefers to the definition
6.2. Novel Analysis Concept 129
and execution of analysis procedures.
Analysis Steps
The idea in this work is to decompose analysis procedures into smaller steps so to increase the
ability to modify them as opposed to monolithic analyses used e.g. in the cell characterization
tool Autochar (see Section 5.5.1). The individual analysissteps can be as simple as the def-
inition of variables or as complex as the determination of the static noise margin. During its
execution in the course of the analysis, each step takes input parameters and generates output
parameters (see runtime data under the heading Analysis Sequencing on p. 130). The output
parameters can be propagated to successive steps so to create dependent steps. By doing so,
constructs like the determination of rise and fall times getpossible where the attainable volt-
age levels for the logic states are derived in one simulationstep and propagated to the actual
timing simulation.
Each step is configured using a graphical dialog. An example of such a dialog in an
implementation of the concept is shown in Fig. 6.3, where a step to derive high/low voltage
and other important parameters from a gate’s voltage transfer characteristic is configured.
Fig. 6.3: Configuration dialog for an analysis step.
By subdividing analysis procedures into smaller steps, questions like “How does the
threshold voltage influence the static noise margin and the rise time?” can be answered. This
is carried out by composing an analysis procedure that consists of a sweep of the threshold
voltage. The sweep carries out the extraction of static noise margin and the rise time (two sub-
ordinate steps of the sweep). In this way, circuit characterization can be used as an exploration
tool.
It can be argued that circuit simulators already provide features for this kind of analysis.
Sophisticated SPICE simulators already contain powerful sweep directives and batch-mode
130 Chapter 6. Analysis Concept
simulations. However, users of these tools have to manuallywrite the testbenches and post-
process the results.
By subdividing analysis procedures into smaller steps, more time is needed to configure
the numerous steps. Consequently, providing specialized analysis programs for each kind of
analysis scenario seems to be more convenient. These programs can contain all necessary
configuration items in one dialog and carry out the simulations as predefined by the program
developer. Moreover, utilization of an external simulatorcan be optimized for maximum
simulation speed because the analysis programs already know in which way the simulator is
used. While this approach is comfortable if only one analysis has to be carried out all the
time, it is not very flexible. If a user wants to change the analysis flow then reprogramming
might be necessary or the original program design has to foresee all sensible modifications to
the standard flow.
Therefore, subdivision of the analysis procedure into smaller steps has been selected in this
work to implement the analysis flow. Existing analyses can bereused as templates for other
analyses. Moreover, no reprogramming of the underlying computer program is necessary if
smaller modifications are introduced to the flow. Analyses can also be cascaded into more
powerful extraction schemes.
Analysis Sequencing
Control of the analysis flow takes place by defining a sequenceof analysis steps to be executed.
The sequence is comparable to a computer script carrying outthe individual steps and is stored
in the data tree in the form of an object called “analysis”. Inthis way, analyses can be treated
like normal data, i.e. can get documentation text or property lists and are stored together with
the data they are used for.
Individual steps of an analysis sequence can propagate results to successive steps by use
of runtime data.Runtime datais a form of dynamic data which only exists during execution
of the analysis procedure. The individual types of runtime data are:
2 Dynamic variables are used for propagating results betweenanalysis steps or for varying
parameters.
2 Dynamic models are dynamic copies of models defined in the data tree. Their purpose
is to allow temporary variations of model parameters in analyses. If e.g. the threshold
voltage of a model shall be varied in an analysis, a dynamic copy of the model in the
data tree is generated and the parameter “threshold voltage” of this dynamic model is
changed in the variation.
2 Dynamic circuits operate similarly to dynamic models. Theyare temporary copies of
6.2. Novel Analysis Concept 131
circuits defined in the data tree. Their introduction allowsvarying parameters of a circuit
without affecting the original circuit definition.
2 Analysis results are the data vectors displayed at the end ofthe analysis. They are
generated and populated during runtime of the analysis.
The analysis sequences are formulated bytree-form scriptswhich define the actual flow. “tree-
form” means that the steps in the sequence are organized as hierarchical trees where the in-
dividual items are described in textual form. Tree-form analysis scripts will also be denoted
asexecution treesin the following. The term “script” refers to the fact that the sequences are
interpreted step by step each time the analysis process is started. The user creates the flow by
instantiating steps in the execution tree. Fig. 6.4 shows a schematic example of an execution
tree.
The individual steps are executed in the order they appear inthe execution tree. Subtrees
are executed before the step following their parent is processed. In Fig. 6.4, steps 3.1 and 3.2
are executed before step 4 is done. Step 3 could be a variable sweep from one value to another
or an optimization loop, etc.
step 2
step 3
step 4
step 3.1
step 3.2
analysis
step 1
Fig. 6.4: Schematic example of a simple execution tree for ananalysis procedure.
With tree-form scripting, analysis procedures can be expressed in an easy-to-read fashion.
Owing to its graphical user interface, tree-form scriptingenables non-expert users to compose
their own procedures without the need to get acquainted witha new scripting language. The
tree-like form is an intermediate form between a true programming language using text scripts
and a graphical programming language oriented toward data-flow modeling.
A programming language using only textual scripts providesthe most powerful description
as the procedures and functions can flexibly be combined. Nevertheless, maintenance and
further development of text scripts requires programming skill and adherence to certain coding
132 Chapter 6. Analysis Concept
styles, i.e. consistent use of names for functions and variables, intense use of comments, etc.
Textual scripting languages include Perl, Tcl, Python, etc.
Data-flow languages describe programs by a graphical flow chart. The chart consists of
functional elements in the form of icons or labeled blocks and connections between them.
The program developer defines the required function by drawing the elements and connections
between them. The connections determine the data flow. Examples of data-flow languages are
LabVIEW from National Instruments [152], Simulink from TheMathworks [153], or Caslon
Flow from Gradual Software [154]. With data-flow languages,non-expert users can develop
programs by drawing flow charts. Moreover, the program already documents the flow in an
intuitive way and visualizes the propagation of data. On theother hand, composing constructs
like switch operations between different options can be difficult to draw. In addition to that,
reading complex flow charts can also be troublesome.
Consideration of both styles (text-based coding and drawing of flow charts) led to the ap-
plication of an intermediate style, viz. tree-form scripting. The flow elements are described
in textual form but are configured using graphical dialogs. The operation sequence is de-
scribed by an execution tree. With this scripting style, thescripting environment is easier to
implement and to use than a text-based scripting system as non-expert users can configure
and alter programs. For small modifications or rearrangements of steps, tree-form scripting is
the most compact description scheme. Moreover, the analysis concept already uses tree-form
descriptions to hierarchically structure analysis data inthe data tree. On the other hand, the
propagation of results from step to step is less intuitive asin data-flow programming. Results
are propagated between steps by use of variables. A step “determine high voltage” would
write its results to the variable “vhigh”. A step “determinedelay time” could then refer to this
variable in order to configure the input waveform needed to extract reasonable delay times.
The mechanisms of using variables are hidden in the configuration dialogs of the individual
steps. The variables are more difficult to track when compared to textual programs or data-
flow drawings. For small programs, tracking the propagationof results is not difficult, but for
larger projects, this might confuse users.
The behavior of the individual analysis steps is programmedin the underlying analysis
framework. Basic analysis steps are:
2 Definition of a variable – defines a variable to be used in subsequent steps. The variable
exists as runtime data until the analysis is finished.
2 Definition of a model – defines a dynamic model to be used in subsequent steps. The
model exists only during runtime of the analysis. It can be used for changing parameters
of existing models in the data tree without affecting the original model.
2 Definition of a circuit – defines a dynamic circuit for use in subsequent steps. The circuit
6.2. Novel Analysis Concept 133
exists only during runtime of the analysis. It can be used fortemporarily changing
parameters of existing circuits in the data tree.
2 Definition of default connectivity – defines what to do with unused terminals in one
of the testbench-generating steps. This directive tells the testbench generator which
values to assign to supply-voltage terminals or to unused input pins of the circuit under
characterization.
2 Sweep a variable – creates a variable, assigns the starting value to it and executes all
steps subordinate to the sweep. After all subordinate stepshave been carried out, the
next sweep value is assigned to the variable, the subordinate steps are again carried out,
etc.
2 Accumulate a vector – creates a data vector for reporting at the end of the analysis.
More sophisticated analysis steps which also involve execution of external simulators include
for example:
2 Analyze the voltage-transfer characteristic of a gate – determine the nominal voltage
for logic high/low state and critical gain of a logic gate. Atruntime, this step constructs
a testbench which contains the gate under characterizationas a series of two instances
in a chain. During execution of the step, a simulator is called to analyze the testbench.
The nominal voltage levels and the critical gain are extracted and reported in runtime
variables. Fig. 6.5 sketches the testbench and the expectedsimulation results for the
VTC determination.
+
−
0
outp
ut v
olta
ge
input voltage
DUT DUT
Vout1 Vout2Vin
Vout1
Vin
Vout2
Fig. 6.5: Schematic of a testbench and expected simulation results for VTC determination.The circles in the voltage plot denote the voltages for the logic states low, unstable, and high.DUT is the device under test, i.e. the gate to be analyzed.
134 Chapter 6. Analysis Concept
2 Analyze ring oscillator – determine the oscillation frequency of a ring oscillator as well
as rise and fall times. A testbench is generated in which the individual gate is mounted
multiple times so to form the ring oscillator. This testbench is used for simulating
the oscillation frequency and extracting timing information of the ring oscillator (see
Fig. 6.6 for a sketch of testbench and expected simulation results).
0 time
osci
llatio
n vo
ltage
DUTDUTDUT
VRO
VLow
VRO
VHigh
Fig. 6.6: Testbench and expected simulation results for analysis of ring oscillators. DUT isthe device under test, i.e. the gate to be analyzed.
2 Determine on and off currents of a transistor device. A single transistor is simulated
and analyzed in order to get on and off currents. The off current is regarded as the
current at maximum magnitude of drain-source voltage and minimum magnitude of
gate-source voltage. The on current is regarded as the current at maximum magnitude
of drain-source voltage and maximum magnitude of gate-source voltage.
2 Determine maximum-square noise margin – extract the maximum square representing
the noise margin of a gate. Details about the determination of the maximum-square
noise margin are presented in Section 5.3.4.
Standardized Execution Interface
Analysis steps are realized in the analysis framework by useof dynamically loadable software
modules. Each module provides a standardized function to create an object-oriented repre-
sentation of the analysis step. The representation contains interface functions to load/setup,
graphically edit, execute, and save the analysis step. The details of the mechanism are specific
to the actual implementation of the analysis framework and will not be detailed here.
6.2. Novel Analysis Concept 135
6.2.4 Simulator Encapsulation
The analysis framework links to circuit simulators by use ofsimulator encapsulation[145].
This technique refers to the integration of simulators intoa design framework in a generic way.
The simulation tool collaborates with the framework through an abstraction layer. This layer
defines a generic interface between the framework and targetsimulators. When a simulator
shall be integrated, no changes to either the framework coreor the simulator are necessary.
Instead, only the interface between them is adapted. The interface provides the following
features:
2 Netlist generation – A generic description of the circuit structure is passed to the in-
terface. The underlying interface code then constructs theappropriate netlist for the
simulator.
2 Simulator control – The simulation process is initiated.
2 Result propagation – The relevant information in the outputfiles of the simulation pro-
cess is transferred to the framework core.
Reasons for introducing simulator encapsulation are:
2 Different research teams utilize different simulator tools. The implementation of the
UML-VRH model disclosed in [65] (see Section 3.2.4.3) employs the circuit simulator
Eldo and models devices with Verilog-A, the analog subset ofVerilog-AMS. Model-
ing in this work was done with the open-source circuit simulator tclspice [155]. This
simulator resorts to the SPICE extension XSPICE [93] and model descriptions com-
piled from C code. In order to be a generic tool, the frameworkhas to disregard the
peculiarities of the individual simulators and has to use a generic interface.
2 Different simulators use different directives to include models. Mentor Graphics’ Eldo
uses they directive to include external models, tclspice and all other XSPICE deriva-
tives use thea directive, while e.g. Tanner T-Spice resorts to thex (or subcircuit)
directive. These differences have to be dealt with in the generation of netlists.
2 Some simulators like the original Berkeley SPICE / XSPICE suite do not support param-
eterizable subcircuits. These are nonetheless needed to provide variation of logic gates
in the course of analyses. The netlist generators of the encapsulation interface have
to translate these parameterized subcircuits into representations suitable for Berkeley
Spice / XSPICE.
2 If modeling systems like VHDL-AMS, Verilog-AMS, or Saber/MAST are used, netlists
are composed in a way different from SPICE. The netlist generator must also deal with
these modeling languages.
136 Chapter 6. Analysis Concept
2 Each simulator has its proprietary format for simulation files. The respective interface
must translate the data into a format readable by the framework core.
In an implementation of simulator encapsulation, a genericinterface is defined. Interac-
tion with simulators takes place by use of this interface. A dedicated implementation of the
interface is provided for each simulator. Netlists are expressed in an intermediate form by
routines of the framework core and transferred to the simulator interface, which in turn gener-
ates the real netlist fed into the simulator. With this two-step approach, simulators can easily
be replaced by other tools. On the other hand, the process of netlist generation is prolonged
because the description has to be translated into the targetformat.
Experimental tests with a prototype implementation of the framework showed that this
translation can affect the time needed to carry out the analysis. This behavior can prolong the
analysis if small circuits are simulated numerous times with tiny variations. A scenario of this
kind is the numerical optimization of circuits. However, the translation process can be sped
up by appropriate programming techniques. Therefore, performance issues are not a major
concern. Moreover, users will not accept the framework if itworks with only one particular
simulation tool. Therefore, the advantages of direct netlist generation were sacrificed to a
more flexible simulator interface.
6.3 Analysis Examples
The purpose of the following sections is to demonstrate the application of the analysis frame-
work in the exploration of OFET-based logic circuits. Basiclogic gates will be evaluated
in the examples using an experimental implementation of themethodology named DCI (De-
sign and Circuit Investigator). The simulations are based on the model parameters derived
in Section 4.3.6. The extraction of performance figures (operational speed, attainable volt-
age values for logic levels, and noise margin) of inverters,NOR gates, and ring oscillators
in current-source configuration is demonstrated. The following definitions for voltage levels
representing logic states will be used:
2 high – The stable voltage level closer to the supply voltage (VDD).
2 low – The stable voltage level closer to zero.
6.3.1 Analysis of an Inverter in Current-Source Configuration
A popular circuit technology implementing logic gates is the current-source configuration
(cf. Fig. 5.1). Currently, it is the method of choice in orderto implement OFET-based logic
circuits. The load element of logic gates in current-sourceconfiguration is a transistor with
6.3. Analysis Examples 137
both gate and source connected to the output. The ratio between the load transistorML and
the driving transistorMD as well as the supply voltage can be varied in order to get optimal
gate performance in terms of circuit speed and robustness.
Analysis Objective
The influence of the geometry ratio between load and driving transistor on the robustness (i.e.
noise margin) and speed of logic gates in current-source configuration shall be investigated.
Circuit speedwill be measured by the oscillation frequency of a ring oscillator and the rise and
fall times of the output of one of its inverters. This approach requires more computation than
traditional timing extraction schemes like simulating theresponse to a step pulse but results
in more realistic waveform shapes.
The following settings shall be used in the analyses:
2 an inverter with load transistor in current-source configuration,
2 both load and driving transistor are p-type conducting and work with the same parameter
set,
2 channel lengthL = 5 µm,
2 channel width of driving transistorWD = 1500µm,
2 channel width of load transistorWL = r × WD, wherer is the ratio between the width
of the load transistor and the driving transistor,
2 supply voltageVDD = -20 V.
Analysis Scripting
The session to analyze inverters in DCI is depicted in Fig. 6.7. The left-hand side of the image
shows the session database. The right-hand side depicts an analysis script for the determina-
tion of robustness and circuit speed for inverters with different width ratios. The database
contains measured devices (in the folder Devices, not expanded in the screenshot), logic gates
in current-source and other configurations (folder Circuits, sub-folder for gates in current-
source configuration expanded), and numerous DCI analysis scripts in the folder Analyses.
The analysis scripts in the example all have names starting with “Analyze VTC for CS-Load
with ...” and are all variations of the same analysis with different models to use in the sim-
ulations. The model configurations used in the analyses willbe explained under the heading
“Impact of Modeling” in the following. The depicted analysis consists of sweeping the ratio
between the load and driving transistor and calculating thefollowing performance figures:
138 Chapter 6. Analysis Concept
2 Nominal voltage levels for logic high and logic low using a pair of identical inverters.
High and low correspond to the stable intersections betweenthe output of the second
inverter and the input voltage.
2 Maximum negative and critical gain of the voltage-transfercurve. The critical gain is
measured at the intersection between the input voltage and output voltage of an inverter.
2 Oscillation frequency of a 15-stage ring oscillator.
2 20% / 80% rise and fall times of an individual stage within thering oscillator. For
calculation of the 20% / 80% thresholds, the voltage swing between the nominal high
and low voltages is used. These voltages were derived above.
2 Unity-gain and maximum-square noise margin.
Fig. 6.7: DCI session to analyze the performance of inverters in current-source configuration.
6.3. Analysis Examples 139
Impact of Modeling
In order to test the influence of inaccuracies of modeling, four combinations of models are
investigated in the analysis:
1. one single table model for driving and load transistor (called combination with table
model, table-based model, or simply otab in the following),
2. one single Linvar model for driving and load transistor (called all-Linvar combination
in the following),
3. the Linvar model for the driving transistor and a Level-1 model exactly mapping the
drain-current curve for zero gate-source voltage (called Linvar/Level-1 combination in
the following),
4. the Level-1 model for the drain-current curve at zero biasand a Level-1 model approx-
imating the output characteristics in the range of zero to -20 V of gate voltage (called
Level-1/Level-1 combination in the following).
The table model was derived by tabulating the original extraction values forKP , VT , andλ
in the Linvar extraction in Section 4.3.6 and using a linear interpolation for theVGS-dependent
values. Model data are listed in Table 6.1.
Table 6.1: Parameter set for table model.VGS[V ] KP [A/V 2] VT [V] λ [V−1]
0 9.9393e-13 8.0 0.0341730670859-4 1.3613e-11 1.8 0.0125761040059-8 2.5627e-11 0.5 0.00735829204921-12 3.4968e-11 -0.2 0.00542531729999-16 4.4147e-11 -1.0 0.00484211159415-20 5.0833e-11 -1.6 0.00453755973153
The parameter set for the Linvar model isKP0 = 8 pA/V2, fk = -2 pA/V3, VT0 = 2.4 V,
fv = 0.2, λ0 = 50 · 10−3 V−1, fl = 0 V−2, R′
par = 10 TΩm. The Level-1 parameters for
the load transistor areKP = 0.994 pA/V2, VT = 8 V, λ = 34.2 · 10−3 V−1. These values
correspond to the line for zeroVGS in Table 6.1. Level-1 parameters for the driving transistor
areKP = 51.6 pA/V2, VT = -2.4 V, andλ = 8.3 · 10−3 V−1. They were derived using least-
squares-fitting. All models used constant gate-drain and gate-source capacitors equivalent to12· Cspec · W · L with Cspec = 0.1 µF/cm2. It is acknowledged that this kind of capacitance
modeling only coarsely describes the capacitive behavior of real devices. More thorough
modeling will also take into account the non-linear nature of device capacitances and the
contribution of layout-related parasitic capacitances.
140 Chapter 6. Analysis Concept
Analysis Results
The set of curves resulting from the analysis is depicted in Fig. 6.8, which also shows the VTC
plot for a width ratio of 8. With the exception of the Level-1/Level-1 combination, the logic
levels for the different model combinations roughly correspond. Owing to the fact that the
least-squares fit for the Level-1 parameters of the driving transistor led to a negative threshold
voltageVT = -2.4 V, the Level-1/Level-1 setup realizes an enhancement/depletion gate leading
to high levels in the range of the supply voltage (≈ −20 V). The critical gains derived by the
all-Linvar combination and Linvar/Level-1 combination also show agreement. The circuit
combination using the table-based model deviates from the other two combinations for ratios
below 6. For the Level-1/Level-1 combination, there is a surge in critical gain due to the
steeper transition between high and low (see Fig. 6.8f). Moreover, the critical-gain point is
situated within the region of steep transition so that the gain is considerably increased.
For the maximum-square noise margin (Fig. 6.8e), the Level-1/Level-1 combination leads
to a considerably larger noise margin than the other combinations. Here, the VTC curve
is shifted to more negative values. The table-based simulation also deviates from the other
two combinations by predicting zero noise margin for ratiosof 4 and below. This can be
understood by inspecting the VTC curves in Fig. 6.8f, where the table-model VTC deviates
from the other VTCs in the range close to zero input voltage. There, the high level of the table-
model VTC does not start to saturate and shows some irregularities at its fix-point (intersection
with the dotted line where the critical gain is measured, seeSection 5.3.5).
Fig. 6.8a+b show the resulting oscillation frequencies andrise/fall times for the transient
simulations of the ring oscillators. Rise and fall times were measured between the 20% and
80% points of the voltage swing from low to high voltage.
The oscillation frequencies correspond to the stage delaytD according totD = 1/(2nfRO),
wheren is the number of inverters in the ring oscillator andfRO is the oscillation frequency.
Considerable deviations between the different modeling combinations can be seen. More-
over, the table-based simulation only yields oscillation at width ratios of 6 and higher. This
corresponds with the observation that there is no noise margin available for the table-based
combination for ratios below 6. The differences in oscillation frequency might exist because
the Linvar model predicts currents which are up to 20% below the measured values for small
|VGS| values. Therefore, this combination yields lowest speed because the load transistor sinks
less current. For the Level-1/Level-1 combination on the other hand, drain currents of the load
transistor are higher so that higher oscillation frequencies can be expected.
6.3. Analysis Examples 141
b)
d)
f)
a)
c)
e)
rise
fall
−20.0
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
−4.0
−2.0
0.0
2 3 4 5 6 7 8 9 10
high
/low
vol
tage
[V] −
−>
ratio of width load/driving trans. −−>
0.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2 3 4 5 6 7 8 9 10
max
.−sq
uare
noi
se m
argi
n [V
] −−
>
ratio of width load/driving trans. −−>
0.5
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
−4.0
−2.0
0.0
2 3 4 5 6 7 8 9 10ratio of width load/driving trans. −−>
5.0m
10.0m
15.0m
20.0m
25.0m
30.0m
2 3 4 5 6 7 8 9 10ratio of width load/driving trans. −−>
0.0m
input voltage [V] −−>
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
2 3 4 5 6 7 8 9 10
freq
uenc
y [H
z] −
−>
ratio of width load/driving trans. −−>
otaball linvar
linvar+lev1lev1+lev1
rise/
fall
time
[s] −
−>
criti
cal g
ain
[V/V
] −−
>ou
tput
vol
tage
[V] −
−>
−20 −15 −10 −5 0
0.0
−2.0
−4.0
−6.0
−8.0
−10.0
−12.0
−14.0
−16.0
−18.0
−20.0ratio width load/drive = 4
Fig. 6.8: Simulated data for an inverter in current-source configuration: a) ring oscillatorfrequency, b) rise/fall times at a particular stage in the ring oscillator, c) nominal high and lowvoltages, d) critical gaingcrit, e) maximum-square noise margins, and f) VTC plot for widthratio of 4. Each plot contains curves for different combinations of simulation models.
142 Chapter 6. Analysis Concept
Analysis Conclusions
By observing the plots in Fig. 6.8, a width ratio of 6 can be identified as an acceptable com-
promise between circuit speed and robustness on one hand andarea usage of the logic gates
on the other hand. A further increase in ratio beyond 6 will also increase the oscillation fre-
quency. However, frequency and nominal voltage levels onlymoderately improve.
Comparison between Gain and Noise Margin
A comparison of Fig. 6.8a and Fig. 6.8d shows that the presence of an oscillation (i.e. a robust
or regenerating operation of inverters in a chain) correlates with|gcrit| > 1. Therefore, it is
interesting to inspectgcrit in order to derive the robustness of a logic gate. In literature on
noise margin calculations, a high|gmax| is also used as a criterion which reflects robustness
of a circuit (e.g. [125]). The relationship between critical gain, maximum negative gain, and
noise margin can be compared using the plots in Fig. 6.9.
a) b)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
2 3 4 5 6 7 8 9 10
gain
[] &
noi
se m
argi
n [V
]
max−square noise margin
−15.0
−10.0
−5.0
0.0
5.0
10.0
15.0
2 3 4 5 6 7 8 9 10
unity gainmax−square
nois
e m
argi
n [V
] −−
>
WL/WD
|gcrit|
WL/WD
|gmax|
Fig. 6.9: Simulation data for noise margin analysis: a) magnitude of critical and most-negativegain together with maximum-square noise margin, b) unity-gain and maximum-square noisemargin. Simulations were done with Linvar/Level-1 combination for driving and load transis-tor.
The magnitude of the critical gain displays a behavior similar to the maximum-square
noise margin while the magnitude of the maximum negative gain vs. the ratio develops differ-
ently. Hence, designs optimizinggcrit lead to different results than designs optimizinggmax.
The unity-gain noise margin also considerably differs fromthe maximum-square data and
even yields negative values (for the low level). Again, designs optimizing the unity-gain noise
margin and the maximum-square noise margin will yield different results. The unity-gain
6.3. Analysis Examples 143
method easily leads to large noise margins for the logic highlevel while negative (i.e. nonex-
istent) noise margins for the logic low level might occur, even for circuits with a critical gain
|gcrit| > 1 and existing maximum-square noise margin. The surge in unity-gain noise margin
for a ratio of four is due to the fact that for smaller ratios, only one unity-gain point exists.
Therefore, the noise margins get very small.
When inspectinggcrit andgmax, these two values strongly depend on the granularity of the
VTC curves from which they are calculated. The two gain values are numerically calculated,
i.e. by finite differences, and therefore strongly depend onthe step size between neighboring
values of the VTC. This leads to the requirement that step sizes should be as small as possible,
e.g. 0.1 V.
Impact of DCI
The analyses presented so far can also be carried out using existing circuit simulators alone.
However, without an integration environment like DCI, the users are required to create and
update the testbenches by hand and to configure batch scriptscontrolling the simulation pro-
cess. Some simulation environments feature the use of scripting systems, e.g. the original
SPICE3 distribution from the University of Berkeley, the simulation environment Synopsys
SaberDesigner, or the simulation tool SimPilot from MentorGraphics. However, these tools
do generally not provide full transparency between different simulation engines. Moreover,
these systems do not automatically generate the required models or testbenches. On the other
hand, cell characterization packages generate testbenches and process simulation results, but
they generally do not explore more basic performance figureslike static noise margin or the
critical gain, or provide heterogeneous analysis plans.
DCI interacts with different simulators, creates analysistestbenches as needed and com-
bines transistor modeling, model and circuit management, analysis configuration, and extrac-
tion of performance figures within a single and interactive user interface. Device and circuit
information, analysis instructions, and analysis resultsare treated as a unit. Moreover, the
users can easily manipulate the complete set of data and scripts.
6.3.2 Analysis of NOR-Gates in Current-Source Configuration
Inverters alone will not make up useful circuits. More complex gates like NORs are required.
The schematic of a NOR gate with the load transistor in current-source configuration is de-
picted in Fig. 6.10. The gate consists of two driving transistorsMD1 andMD2 in parallel and
a load transistorML in current-source configuration. The driving transistors are controlled by
the two inputsVin1 andVin2, respectively. For NOR3 gates in current-source configuration, a
third driving transistorMD3 would be added in parallel toMD1 andMD2.
144 Chapter 6. Analysis Concept
ML
MD1 MD2 Vout
Vin2Vin1
VDD
Fig. 6.10: Schematic of a two-input NOR with load transistorin current-source configuration.
Analysis Objective
A simple analysis of a two-and a three-input NOR with a load transistor in current-source
configuration shall be carried out. The driving transistorsshall have identical widths as defined
by WD1 = WD2 = WD. The width of the load transistorML shall be varied with respect to
WD so thatWL = r · WD. In the course of the analysis, the VTC and transient behavior is
inspected by the methods already presented in Section 6.3.1. One input shall be used for the
characterization while the nominal low voltageVlow shall excite the remaining input(s).Vlow
shall also be varied.
Analysis Scripting
The analysis session to analyze NORs in DCI is similar to the inverter-related session depicted
in Fig. 6.7. Differences are the use of NOR2 or NOR3 gates as circuits under test and terminal
“in1” as characterization input. The other inputs “in2” and“in3” (if available) are set to a value
Vlow using the “define connectivity” instruction.Vlow is added as a second parameter to sweep,
i.e. in an outer loop.
Analysis Results
The results of the analysis are presented in Fig. 6.11. For the calculations, the transistor model
from Section 4.3.6 was used. The data demonstrates that the anticipated low levels strongly
influence the choice ofWL. The analysis can be used for finding the maximum tolerable low
level |VLow| for a particular design. This voltage depends on device parameters but also on
the fan-in, i.e. the number of inputs of a gate. This is demonstrated in Fig. 6.12, where a two-
input NOR gate and a three-input NOR gate with identical transistor dimensions are compared
6.3. Analysis Examples 145
at a fixed supply voltage of -20 V and a low voltageVLow = -2 V.
−3 V−4 V
−3 V−4 V
−3 V −4 V
−3 V
−4 V
−4 V−3 V−2 V
rise
fall
a)
c)
b)
d)
NOR2INV
2.0m
4.0m
6.0m
8.0m
10.0m
12.0m
14.0m
16.0m
18.0m
2 4 6 8 10 12 14ratio of width load/driving trans. −−>
0.0m
−3.5
−3.0
−2.5
−2.0
−1.5
−1.0
0.0
2 3 4 5 6 7 8 9 10ratio of width load/driving trans. −−>
−0.5
−20.0
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
−4.0
−2.0
0.0
2 3 4 5 6 7 8 9 10
high
/low
vol
tage
[V] −
−>
ratio of width load/driving trans. −−>
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
2 3 4 5 6 7 8 9 10
freq
uenc
y [H
z] −
−>
ratio of width load/driving trans. −−>
rise/
fall
time
[s] −
−>
criti
cal g
ain
[V/V
] −−
>
Vlow = -2 V
Vlow = -2 V
Vlow = -2 V
Vlow = -2 V
Fig. 6.11: Simulated data for inverters and NOR2 gates with load transistor in current-sourceconfiguration: a) ring oscillator frequency, b) rise/fall times, c) nominal high and low voltages,d) critical gain. The second input of the NOR gate was biased with Vlow = -2/-3/-4 V.
Analysis Conclusions
The simulation results in Fig. 6.11 and Fig. 6.12 show that the fan-in (FI) strongly influences
the attainable circuit speed and high levels. Increasing the width ratio of NOR gates does
not compensate for the detrimental effect of FI in comparison to the simple inverter. For the
transistor type used in this section, NOR2 gates should havea ratio of at least 8 and NOR3
gates of at least 10.
146 Chapter 6. Analysis Concept
a)
c)
rise
fall
b)
d)
NOR3NOR2
INV
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
2 4 6 8 10 12 14
freq
uenc
y [H
z] −
−>
ratio of width load/driving trans. −−>
2.0m
4.0m
6.0m
8.0m
10.0m
12.0m
14.0m
16.0m
18.0m
20.0m
2 4 6 8 10 12 14ratio of width load/driving trans. −−>
0.0m
−4.0
−3.5
−3.0
−2.5
−2.0
−1.5
−1.0
0.0
2 4 6 8 10 12 14ratio of width load/driving trans. −−>
−0.5
criti
cal g
ain
[V/V
] −−
>ris
e/fa
ll tim
e [s
] −−
>
−20.0
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
−4.0
−2.0
0.0
2 4 6 8 10 12 14
high
/low
vol
tage
[V] −
−>
ratio of width load/driving trans. −−>
Fig. 6.12: Comparison of simulation results for inverters and NOR2/NOR3 gates withVDD = -20 V: a) ring oscillator frequency, b) rise/fall times, c)nominal high and low volt-ages, d) critical gain. Unused inputs were biased withVlow = -2 V.
6.3.3 Analysis of Parameter-dependent Gate Behavior
In the examples presented so far in Section 6.3, the analysisdoes not depend on the model
type. The analysis framework can also be used for predictingdirections for material opti-
mization. This is carried out by deliberately varying critical model parameters and inspect-
ing resulting circuit performance. In this section, variation results obtained from DCI sim-
ulations are presented. The analysis is carried out using the simplified Linvar model from
Section 4.3.6.
6.3. Analysis Examples 147
Analysis Objective
The proper function of a NOR gate at a given supply voltageVDD in the presence of off-current
variations shall be verified. This is done using ring oscillator frequencies and the critical gain.
The same ring oscillator configuration as in Section 6.3.1 isused. For demonstration purposes,
the analysis is restricted to the treatment of off-current variations. In principle, analysis of the
impact of on-current variation, threshold-voltage variation, etc. can be done with similar
approaches.
Analysis Scripting
The analysis consists of varying the “off current”Ioff , i.e. the drain current at maximum
magnitude of drain-source voltage and zero gate-source voltage, while keeping constant the
“on current”Ion, i.e. the drain current at maximum magnitude of drain-source and gate-source
voltage. In the Linvar model, this can be accomplished by varying KP0 and calculatingfK in
such a way thatKPmax remains unchanged. The corresponding formula forfk is
fk =KPmax − KP0
VGS,max, (6.1)
whereKPmax is the conductance parameter at the maximum|VGS,max|, i.e. the gate-source
voltage for the “on current”.
Fig. 6.13 shows the DCI script for the analysis. The calculations corresponding to (6.1)
are outlined by boxes. The runtime variables kp0 and fk are used as mapping parameters for
the models describing the load and driving transistors, respectively.
Analysis Results
Fig. 6.14 shows the simulation results. The data suggests that Ioff strongly influences critical
gain, circuit speed, and attainable voltage level for logichigh. A weaker influence on the low
level is observed because the VTC range for the logic low voltage is relatively large (see e.g.
Fig. 6.8f) so that a degenerate high level is not so crucial for the low level. For a ratio of 6, the
ring oscillator ceases to function with a zero-based process conductance of 12 pA/V2, where
the on/ratio dropped to a value below 200.
148 Chapter 6. Analysis Concept
Fig. 6.13: DCI script to analyze the influence of off-currentvariation on circuit performance.
6.4. Chapter Summary 149
c)
a)
d)
b)
150.0
200.0
250.0
300.0
350.0
400.0
450.0
500.0
550.0
600.0
0p 2p 4p 6p 8p 10p 12p 14p 16p
−3.5
−3.0
−2.5
−2.0
−1.5
−1.0
0p 2p 4p 6p 8p 10p 12p 14p 16p
−0.5
ratio = 6
ratio = 8
criti
cal g
ain
[V/V
] −−
>
zero−based process conductance [A/V²] −−>
on/o
ff ra
tio −
−>
zero−based process conductance [A/V²] −−>
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
0p
ratio = 6
ratio = 8
−18
−16
−14
−12
−8
−6
−4
−2
0
6p 8p 12p 14p 16p
ratio = 6
ratio = 8
zero−based process conductance [A/V²] −−>
zero−based process conductance [A/V²] −−>
freq
uenc
y [H
z] −
−>
nom
inal
hig
h/lo
w v
olta
ge [V
] −−
>2p 4p 6p 8p 10p 12p 14p 16p
0p 2p 4p
−10
10p
Fig. 6.14: Simulations of two-input NORs with varying zero-based process conductanceKP0
for two ratios (6 and 8): a) critical gain, b) oscillation frequency, c) on/off ratio of the drivingtransistor, and d) nominal high and low voltages.
6.4 Chapter Summary
In this chapter, a novel analysis concept was discussed. Thebasic idea of the concept is to
combine data management, modeling, and circuit investigation in a single analysis framework.
Data is organized in a hierarchical data tree where all itemsrelevant in the analysis (model
data, model sets, circuits, analysis scripts, results) canbe stored. Analysis procedures are
described by use of tree-form scripting in which the flow of commands is expressed using
execution trees. Individual actions, i.e. analysis steps,are configured using graphical dialogs.
150 Chapter 6. Analysis Concept
Simulation tools are integrated into the framework via an abstraction layer which provides a
standardized interface.
The analysis framework resolves the following issues with existing tools (cf. p. 122):
1. A single software environment is provided. It is easy to use and allows the users to focus
on carrying out their analysis in a highly automated way. Theenvironment features a
graphical user interface and easy access to all relevant data of the analysis.
2. The environment integrates modeling of transistor devices by use of model extractors,
which are fully integrated into the framework.
3. The environment provides automatic netlist generation for various performance analy-
ses (noise margin detection, circuit speed, etc.).
4. Preconfigured analysis procedures and libraries of logicgates can be stored in the
database of the analysis environment and reused in later analyses.
5. The environment tracks all model references in the circuits used by the netlist generator.
Arbitrary models can be mapped to the references used in these circuits.
6. Analysis procedures are expressed as execution trees where all individual steps can be
configured using graphical dialogs. Different analysis steps exist to define variables,
perform sweeps, map models and circuits, or to carry out sophisticated simulations.
This setup allows flexible manipulation and extension of existing analysis schemes.
7. During the analyses, model and circuit parameters can be flexibly varied so to provide
means of exploring the parameter-dependent behavior of devices and circuits. New
schemes can be defined by composing the respective executiontrees.
8. The environment automatically collaborates with external simulators by calling these
tools via an abstraction interface. If the simulation tool is replaced, only an implemen-
tation of the interface to the replacing simulator is required.
151
Chapter 7
Summary and Further Work
This chapter summarizes the work presented in this thesis and discusses possible extensions
to the provided methods, analyses, and tools.
7.1 Summary
Organic field-effect transistors (OFETs) are currently in the early stages of process develop-
ment and device optimization. In the course of optimization, circuit simulation of reasonable
application circuits is a key point in fine-tuning the deviceparameters of OFET technologies
as it provides insight into the performance potential of given or hypothetical OFET genera-
tions. However, many issues have to be overcome before circuit analysis by circuit simulation
can unfold its full potential in the field of OFET-based circuits. Owing to the early stages in
the field, adequate transistor models, modeling software, and analysis tools (proper perfor-
mance figures, simulation software) dedicated to organic electronics are missing. Therefore, a
computer-aidedmethodology to analyze the performance of OFETs in logic circuitshas been
developed in this work. The basic idea of the concept is to provide anintegrated environment
for data management, transistor modeling, and the automatic analysis of benchmark circuits.
In order to implement the methodology, issues in OFET modeling and circuit characterization
were analyzed in this work.
In the part dealing withOFET modeling, a model quality chart was defined so to allow
formal comparison of individual modeling approaches. By using the model quality chart,
model accuracy, proper capacitance modeling, compactnessof a model, parameter extraction,
and modeling of stress effects are rated. Existing modelingapproaches for OFET devices,
extraction procedures for the respective parameters, and extraction tools were discussed. A
review of the tools showed that they are either very general or specialize on certain models.
The tools cannot visualize which model type can best fit a given transistor. Therefore, users
152 Chapter 7. Summary and Further Work
have to carry out parameter extractions for different modeltypes and have to compare the
resulting model accuracies in order to find the most-appropriate model. In order to facilitate
modeling, a novel extraction scheme calledVSat method was therefore developed in this work.
The approach is used for extracting the basic parameters threshold voltage (VT ), process con-
ductance (KP ), and channel length modulation (λ) for individual ID vs. VDS curves. The
VGS-dependence of these parameters is used for identifying appropriate model types because
each type has characteristicVGS dependences for the basic model parameters. Two models
were presented which directly use the basic parameters extracted with theVSat method: a
table model and an analytic model called Linvar model.
In the part dealing with thecircuit characterization, a novel approach was introduced
which defines the robustness of logic gates by inspecting thegain of the fix point in the
voltage-transfer characteristic. An existing method of qualitatively defining the compatibility
of valid logic level ranges was extended to yield noise margins.
Traditional methods of defining static and dynamic performance figures of basic logic
circuits were analyzed. Existing tools for circuit characterization were reviewed. Like in
the case of modeling, these tools are either very general or specialize on a limited set of
applications. Many tools lack automatic testbench generation, inclusion of documentation, or
flexible manipulation of the analysis flow and data. Seamlessintegration of device modeling
is generally not provided.
In view of the drawbacks of existing modeling and characterization tools, a novel analysis
methodology was developed in this work. The concepts of the methodology are:
2 Transistor modeling and circuit characterization are integrated into a single environ-
ment.
2 The users have direct access to all items needed in the modeling and characterization
steps (models, circuits, waveforms, analysis procedures).
2 The items are organized in a data tree and can be arranged hierarchically according to
the needs of the users.
2 Documentation and a property set can be assigned to each itemin the data tree. This
facilitates reuse of existing analyses and backtracking ofunexpected results as every
item can be thoroughly described.
2 Automation of the analysis is reached using a graphical scripting concept that allows
non-expert users to compose new or reuse existing analysis procedures.
2 Testbenches to analyze typically used performance figures like circuit speed or robust-
ness, i.e. noise margin, are generated fully automatically. The generation process and
result extraction seamlessly integrate into the graphicalscripting concept.
7.2. Further Work 153
Scientific progress could be made in this work in the formal comparison of models and
in the extraction of model parameters by use of the novelVSat method. Novel model types
for OFET devices and a computer-aided methodology for OFET-based modeling and circuit
characterization have been developed.
7.2 Further Work
This section summarizes methodological and practical issues which have not been resolved in
the design of the analysis concept presented in Chapter 6 or its experimental implementation,
DCI.
Modeling
TheVSat method could be used for generating amodeling wizard. Such a wizard is a program
which analyzes available transistor data and provides different action routes on the basis of
the analysis results. The wizard will run through a number ofsteps until a proper model has
been selected and the accompanying parameter sets have beenderived. In future work, proper
models could be chosen according to theVGS-dependent shapes of the extracted parameters.
The process could be automated by use of shape-detection algorithms. Alternatively, the basic
parameters could be used as initial values for curve fitting.
Another issue is the separation of contact effects during parameter extraction. There have
been reports on the treatment of contact effects in transistor modeling but the extraction pro-
cedures often require interference by the user. Methods like the Unified Extraction Method
(UEM) [56] could help in the extraction of contact effects. Additionally, UEM is also very
interesting for model extraction in general because it is specifically designed for thin-film
transistors. However, UEM requires a sophisticated user interface and a high degree of user
interaction. Here, efficient implementations and automation schemes for selecting appropriate
current-voltage curves could be explored in further work.
Statistical modeling of OFET-based measurement series is currently not included in the
data organization scheme of the analysis concept. However,statistical analyses are important
for more realistic simulations of device performance in integrated circuits.
Capacitance modeling is currently approximated by constant capacitors in the analyses
presented in this work. The influence of nonlinear capacitances on simulation results for ring
oscillators needs to be investigated. Such nonlinear capacitances are included e.g. in models
for variable range hopping [63, 65].
There have been efforts to analytically explain the subthreshold behavior of OFETs [64] in
the framework of variable range hopping. A proper description of this operation region could
154 Chapter 7. Summary and Further Work
improve the accuracy of simulating NAND gates or transmission gates. However, research on
this topic is still in the early stages.
Circuit Characterization
Automatic circuit sizing is currently not addressed by DCI,the experimental implementation
of the methodology. Therefore, it is up to the user to providesensible transistor configurations
for their circuits under analysis. Generic circuit sizers could be included in the implementation
of the analysis concept by providing appropriate commands to the graphical scripting system.
The special needs and techniques of statistical circuit analysis have currently been disre-
garded in the design of the analysis concept. In spite of that, statistical variation is important
in order to provide realistic data on the performance potentials of OFET-based circuits. Yet,
there is currently only small activity in the research community regarding statistical methods
in the characterization of OFET-based logic circuits. Approaches like the method of equi-
librium zones (MEQ) could be used in conjunction with statistical methods. The statistical
analyses would establish upper and lower bounds for the VTC curves.
155
Appendix A
List of Symbols
Symbol Description Unit
α effective overlap parameter between localized states in
VRH modeling
Å−1
α power factor forVGS-dependence ofID in TFT modeling
and UEM
–
αsat saturation variation parameter in Psi-TFT modeling –
β device conductance parameter of a transistor A/V2
β ratio between effective grain-boundary size and channel
length in Psi-TFT modeling
–
∆E voltage-dependent contribution to extraction functionE in
SJ method
V/A
ε0 free-space permittivity constant (8.854187818 · 10−12) AsV−1m−1
εr relative permittivity of the insulator –
εs relative permittivity of the semiconductor –
η diode ideality factor –
ηi subthreshold ideality factor in Psi-TFT modeling –
γ power parameter for a-Si TFT mobility –
γ fitting parameter for conductivity in UML modeling –
λ transistor channel-length modulation V−1
λ0 constant channel-length modulation in Linvar modeling V−1
µ carrier mobility cm2/V·sµ0 upper mobility limit in Psi-TFT modeling cm2/V·sµ1 low-field mobility in Psi-TFT modeling cm2/V·sµeff effective mobility cm2/V·s
156 Appendix A. List of Symbols
Symbol Description Unit
µg grain intrinsic mobility in Psi-TFT modeling cm2/V·sµgb mobility at grain boundary in Psi-TFT modeling cm2/V·sµn mobility of electrons cm2/V·sµp mobility of holes cm2/V·sµs subthreshold mobility in Psi-TFT modeling cm2/V·sσ conductivity S/cm
σ0 prefactor for conductivity in VRH modeling S/cm
τ(VGS) delay function in Dresden modeling –
τs statistical shift parameter for delay function in Dresden
modeling
–
a mobility factor in Hamburg VRH modeling cm2/V·sai fitting parameter for shape functionf in Dresden modeling –
b power factor for mobility in Hamburg VRH modeling –
bi fitting parameter for shape functionf in Dresden modeling –
Bc critical number of bonds per site in largest cluster of a per-
colation system
–
CGD gate-drain capacitance F
CGS gate-source capacitance F
ci fitting parameter for scale functionh in Dresden modeling –
Cis insulator capacitance per unit area F/cm2
di fitting parameter for scale functionh in Dresden modeling –
E(VGS − VT ) extraction function for contact resistance in SJ method V2/A
E0 constant contribution to extraction functionE in SJ method V2/A
Eb barrier height at grain boundary in TFT modeling eV
EC energy of lower edge of conduction band eV
EF Fermi energy eV
EV energy of upper edge of valence band eV
f(V ) VTC of gate under consideration in unity gain method V
f(VDS) shape function in Dresden Modeling –
F1(x) VTC curve of gate under consideration in method of maxi-
mum squares
V
F2(y) inverse VTC curve of gate under consideration in method
of maximum squares
V
fλ factor forVGS-dependent channel-length modulation in Lin-
var modeling
V−2
157
Symbol Description Unit
fk factor forVGS-dependent process conductance in Linvar modeling A/V3
fT factor forVGS-dependent threshold voltage in Linvar modeling –
G0 length-independent channel resistance of transistor Ω/m
gcrit critical gain at fix point of VTC curve of a logic gate –
gd drain conductance S
gm transconductance S
gmax maximum negative gain of VTC curve of a logic gate –
H(VGS) extraction function in UEM for TFTs V
h(VGS) scale function in Dresden modeling –
I current A
I00 current density in cut-off region of UML modeling A/m
Ia above-threshold current in Psi-TFT modeling A
ID drain current A
IDMax maximum current inVSat extraction A
IDS0 saturation current clear of channel-length modulation inVSat ex-
traction
A
IDSat current at transition between linear and saturation region A
Ileak subthreshold leakage current A
IS saturation current of Schottky diode A
Isub sub-threshold current in Psi-TFT modeling A
K conductance parameter in UEM extraction for TFTs S
K fitting parameter for mobility in UML modeling S
K ′ fitting parameter for conductivity in UML modeling S
kB Boltzmann constant (1.380662 · 10−23) VAs/K
KG geometry factor in Dresden modeling A
KP process conductance parameter of a transistor A/V2
KP0 constant process conductance factor in Linvar modeling A/V2
KS statistical current scale factor in Dresden modeling –
L length of the transistor channel m
Ln length of electron-accumulating region in ambipolar transistors m
Lp length of hole-accumulating region in ambipolar transistors m
m power factor for mobility in UML modeling –
mµ mobility parameter in Psi-TFT modeling –
158 Appendix A. List of Symbols
Symbol Description Unit
n number of grain boundaries along channel in Psi-TFT modeling –
NA doping-induced charge density in UML modeling –
NMH noise margin for high level of a logic gate V
NML noise margin for low level of a logic gate V
Nt density of localized states in VRH modeling cm−3
pi fitting parameter for delay functionτ in Dresden modeling –
q elementary charge (1.6021892 · 10−19) As
QD drain charge of transistor C
QG gate charge of transistor C
qi fitting parameter for delay functionτ in Dresden modeling –
QS source charge of transistor C
r step function –
RC contact resistance Ω
RCD compensation resistance for drain-side contact resistance Ω
RCS compensation resistance for source-side contact resistance Ω
RD drain-side contact resistance (synonymous toRDC) Ω
RDC drain-side contact resistance (synonymous toRD Ω
RM effective channel resistance including contact effects Ω
Rpar bulk resistor in Linvar-type OFETs Ω
R′
par width-independent bulk resistor in Linvar-type OFETs Ω · mRS source-side contact resistance (synonymous toRSC) Ω
RSC source-side contact resistance (synonymous toRS) Ω
S subthreshold slope V/dec
T temperature K
T0 width of exponential distribution in VRH modeling K
tdf high-to-low delay of logic gate s
tdr low-to-high delay of logic gate s
tf fall time of of logic gate s
tis insulator thickness m
159
Symbol Description Unit
tPD pair delay of two identical gates s
tr rise time of logic gate s
u, v coordinates of rotated coordinate system in method of maximum
squares
V
V voltage V
VAA characteristic voltage for mobility in a-Si TFT modeling V
VB potential barrier between grains in Psi-TFT modeling V
VD drain voltage V
VDD supply voltage V
VDMax maximum (in magnitude) drain current inVSat method V
VDS drain-source voltage (VD − VS) V
V ′
DS drain-source voltage clear of contact effects V
VDSat saturation voltage (synonymous toVSat) V
VG gate voltage V
VGDT VG − VD − VT V
VGS gate-source voltage (VG − VS) V
V ′
GS gate-source voltage clear of contact effects V
VGST effective gate-source voltage (VG − VS − VT ) V
VGST effectiveVGST clear of contact effects V
VH stable voltage level for logic high in VTC curve of a logic gate V
160 Appendix A. List of Symbols
Symbol Description Unit
VIH,min minimum allowable voltage level for logic high at the input of a
logic gate
V
VIL,max maximum allowable voltage level for logic low at the input ofa
logic gate
V
Vin input voltage of a logic gate V
VL stable voltage level for logic low in VTC curve of a logic gate V
VM metastable voltage level in VTC curve of a logic gate V
VOH,min minimum allowable voltage level for logic high at the outputof a
logic gate
V
VOL,max maximum allowable voltage level for logic low at the output of a
logic gate
V
VON on voltage V
VON statistical quantity to shift switch-on voltage in Dresdenmodeling V
Vout output voltage of a logic gate V
VS source voltage V
VSat saturation voltage (synonymous toVDSat) V
V ′
Sat saturation voltage clear of contact effects V
VSO switch-on voltage V
VT threshold voltage V
V ∗
T effective threshold voltage including contact effects V
VT0 constant threshold voltage parameter in Linvar modeling V
VT,n threshold voltage of electron-accumulating region of ambipolar
transistor
V
VT,p threshold voltage of hole-accumulating region of ambipolar tran-
sistor
V
Vth thermal voltage V
Xτ power factor for delay functionτ in Dresden modeling –
Xf power factor for shape functionf in Dresden modeling –
Xh power factor for scale functionh in Dresden modeling –
W width of the transistor channel m
161
Appendix B
List of Acronyms
a-Si TFT amorphous silicon thin-film transistor
BC bottom contact
BFL Buffered FET Logic
CMOS complementary metal oxide semiconductor
CSL current-source load
DCI Device and Circuit Investigator
DL diode-load
DUT device under test
E/D logic enhancement-depletion logic
EDA electronic design automation
F8T2 poly(9,9-dioctylfluorene-co-bithiophene); short: polyfluorene
FET field-effect transistor
FI fan-in
FO fan-out
GND ground
IC integrated circuit
IGFET insulated-gate field-effect transistor
KCL Kirchhoff Current Law
MOSFET metal oxide semiconductor field-effect transistor
MQC Model Quality Chart
MTR multiple trapping and release
OFET organic field-effect transistor
OLED organic light-emitting diode
OTFT organic thin-film transistor
P3HT poly(3-hexylthiophene)
PDHTT poly(3,3”-dihexyl-2,2’:5’,2”-terthiophene)
162 Appendix B. List of Acronyms
PEDOT/PSS poly-(ethylenedioxy-thiophene)/poly(styrene sulfonic)acid
PPV poly(phenylenevinylene)
Psi TFT polycrystalline silicon TFT
PTAA polytriarylamide
PTV poly(2,5-thienylen vinylene)
RFID radio-frequency identification
RO ring oscillator
RPI Rensselaer Polytechnic Institute
SPICE simulation program with integrated circuit emphasis
TC top contact
TFT thin-film transistor
UEM Unified Extraction Method (→ UMEM)
UMEM Unified Model and parameter Extraction Method (→ UEM)
UML universal mobility law
VRH variable range hopping
VTC voltage transfer characteristic
163
Appendix C
Glossary
analysis/analysis sequence/analysis procedure/analysis flow The four terms refer to a se-
quence of operations carried out to study the characteristic behavior of a circuit or de-
vice.
benchmark circuit A circuit useful in the extraction of typical performance figures of de-
vices. In the domain of logic circuits, inverters, ring oscillators, flip-flops, counters, etc.
might be used.
characterization Process of extracting performance figures of a circuit (circuit characteriza-
tion) or model parameters of a device (device characterization).
circuit This term refers to a combination of two or more devices whichcarries out a useful
function, i.e. acts as a logic gate, amplifier, etc.
conjugation In chemistry, a system of covalently bonded atoms in a compound with an alter-
nation of single and multiple bonds [9].
device One of the basic electrical elements supported by a semiconductor technology (tran-
sistor, resistor, capacitor, etc.). In this work, the term mainly refers to transistors.
effective mobility Seemobility.
flexography printing A printing process where ink is transferred from a raised area. The
printing plate is made of a flexible material.
flip-flop A memory element where the level changes of the inputs define the stored state, i.e.
a edge-triggered memory element [134] as opposed to level-sensitive latches. See also
latch.
164 Appendix C. Glossary
framework A software tool in which analysis projects can be developed and organized. The
framework integrates the various tools needed in the analysis process. The termsanal-
ysis environment, analysis framework, andanalysis conceptare used synonymously.
gravure printing A printing process where ink is transferred from a recessed surface.
latch A memory element where the levels of the inputs define the stored state, i.e. a level
sensitive memory element [134] as opposed to edge-triggered flip-flops. The simplest
form of a latch is the so-called RS latch which consists of twocross-coupled two-input
NAND or NOR gates, respectively (see Fig. D.2). See alsoflip-flop.
mobility This quantity (unit cm2/Vs) describes the mobility of charge carriers. Several types
of mobilities can be defined (see [83]). In this work, the gate-voltage-dependent effec-
tive mobility, derived from experimental current-voltagecharacteristics of a FET [52],
is used.
model The representation of the electrical behavior of a device useful in circuit simulation.
A model consists of a description of the electrical behaviorin the form of equations
(analytical modelor compact model) or a combination of devices (macro model) as
well as a set ofmodel parameters.
noise Any deviation from nominal voltages [112]. Sources for noise can e.g. be [113] spu-
rious signals/crosstalk which interfere with information-carrying circuit nodes, or in-
herent fluctuations of device parameters owing to fabrication process or operating point
variations.
off current Current at maximum magnitude of drain-source voltage and minimum magnitude
of gate-source voltage. See alsoon current.
on current Current at maximum magnitude of drain-source voltage and maximum magnitude
of gate-source voltage. See alsooff current.
output characteristics Plot of the drain current vs. drain-source voltage of a transistor.
percolation theory This field studies properties of disordered systems like conductivity by
means of statistical methods [156]. In organic electronics, percolation theory is used to
analyze transport in inhomogeneous organic semiconductors.
performance figures Figures representing the performance of a circuit or devicein a certain
application. Performance figures can be switching speed, power consumption, robust-
ness against parameter variation, etc.
165
polymer A compound consisting of organic chains. The length of the chains is not clearly
defined [9].
ring oscillator A chain of inverting gates forming a loop with an odd number ofstages. The
output of each gate is connected to the input of its successor. The output of the last gate
is fed back to the input of the first gate. This configuration leads to an oscillation with a
frequency off ≈ 2ntD wheren is the number of stages andtD is the delay per stage.
screen printing A printing process where ink is applied to a surface through afine mesh
screen. The image is defined by blocking parts of the mesh screen [23].
testbench/test circuit A combination of one or more benchmark circuits together with the
required input signals and output loads. The testbench is used to derive performance
figures of devices or circuits during circuit characterization.
thin-film transistor A type of transistor where the semiconducting channel is deposited as a
thin film.
transfer characteristic Plot of the drain current vs. gate-source voltage of a transistor.
trap An energy level within the bandgap of a semiconductor due to the presence of impurities
or structural defects [14].
voltage transfer characteristic (VTC) Plot of the output voltage vs. input voltage of a logic
gate.
166 Appendix C. Glossary
167
Appendix D
Symbols and Truth Tables for Logic
Circuits
Logic Gates
A QL HH L
AB Q&
AB Q
A B QL L HL H HH L HH H L
L H L
A B QL L H
H L LH H L
BA Q
BA Q
BA Q
Inverter
A B QL L HL H LH L LH H H
XNORAB Q
Q QA
NAND
NOR
A
Gate Type Truth Table(EAN) Symbol
European North−American
(ANSI) Symbol
Fig. D.1: European/american symbols and truth tables for selected logic gates.
168 Appendix D. Symbols and Truth Tables for Logic Circuits
Latches
&
&
a)
b)
L LL
LHH H
L LL
LH
HH H
HLX
XLH
H
Q
Q
R
SR
S Qn+1
Qn
Qn+1
QnQ
R
S
R
S
Q
Fig. D.2: Schematics and truth tables for latches: a) NOR-based, and b) NAND-based.
169
Appendix E
Simulation Software
The following software tools have been used during the experimental analyses and for the
implementation of the analysis framework:
2 the SPICE simulatorTclSpice(available at http://tclspice.sf.net) for the simulationof
logic gates and circuits,
2 the numerical languageGNU Octave(available at www.gnu.org/software/octave) for
the postprocessing in modeling issues,
2 the scripting languagePython(available at www.python.org) for the implementation of
DCI, the experimental implementation of the analysis concept,
2 the C++ class librarywxWidgets(available at www.wxwidgets.org) for the implemen-
tation of the graphical user interface
2 the numerical C libraryLevmar(available at http://www.ics.forth.gr/∼lourakis/levmar/)
for the implementation of a Levenberg-Marquardt optimizer
170 Appendix E. Simulation Software
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