ltcc designltcc design ltcc example 2 microwave office Ł the rf transitions are simulated using an...

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. . . . . . . . . . . . . . . . . . . . . . . . . . . .LTCC DESIGN

LTCC RECEIVER FRONT END OVERVIEW

The �receiver ltcc v5 NEW.emp� project demonstrates the current capabilities of Microwave Office in designing LTCC (Low Temperature Cofired Ceramic) circuits without the need for special elements or libraries. This application note illustrates the tight integration of various simulations such as EM, Linear, Har-monic Balance (HB) circuit level, and HB behavior level with the layout. This integration is key to increasing a designer�s efficiency from design through phys-ical implementation (layout).

Figure 1. 3D View of a Receiver Front End Implemented in LTCC

The subsystem is designed using several simulation technologies and two differ-ent layout processes:

� The low noise amplifier (LNA) was designed in an HBT IC process using linear simulations.

� The Lo buffer amp is designed in an LTCC process using HB simulation.

� The mixer is simulated using an HB Behavioral model, and implemented with a package part that is drawn as artwork.

M i c r o w a v e O f f i c e 1

L T C C D E S I G N

LTCC Example

� The RF transitions are simulated using an EM solver, and the layout in EM is mapped to the layout for the complete circuit.

� The buried spiral inductors are simulated in the EM solver and then extracted to an equivalent linear model. The layout for the spiral is implemented as a combination of a parameterized layout cell and a fixed artwork cell for the air bridge.

The Microwave Office layout tool allows great flexibility in layout. A designer can have Layout versus Schematic implementation, artwork cells, and drawn shapes all reside in the same layout. Some of the key layout features are:

� Parameterized layout cells for microstrip lines, stripline, and spirals

� Parameterized artwork cell creation for a thin film resistor

� Fixed artwork cells for packaged parts, resistors, capacitors, and transistors

� Drawing tools to create traces, pads, and via arrays

� A 3D view to resolve interference issues for vias, pads, and lines on different layers.

LTCC EXAMPLE

This application note focuses on the physical implementation of an RF sub-system. Circuit design issues are excluded except for cases involving the physical implementation, such as RF transitions between layers. LTCC reduces the size of the packaging for this Receiver front end subsystem. To shrink the layout, integration is done vertically, and circuit elements like spirals, capacitors and resistors are buried in layers beneath the traces that interconnect the IC chip and packaged parts. The design process is summarized as follows:

1. Create a layout process file (*.LPF).

2. Create artwork cells for circuit elements and packages.

3. Create via cells and via arrays.

4. Create a model and layout cell for buried spirals.

5. Simulate RF transitions with EM, and map the EM structure to a layout.

6. Assign artwork cells to schematic elements.

2 M i c r o w a v e O f f i c e

L T C C D E S I G NLTCC Example

7. Route trace lines for interconnects between elements.

8. Place via fences and via arrays for RF isolation and ground planes.

9. Export Gerber files and drill files.

Creating a Layout Process FileThe layout process file (*.LPF) defines the default settings for the drawing lay-ers, layer mappings, export mappings, EM mapping, drill tool definition, and 3D view of the layout. In this example, the IC and LTCC layout processes are com-bined into one process. To view the layout properly, the RFIC process must be combined with the LTCC process.

All of the properties in an LPF file (with the exception of line types) can be set by double-clicking the Layer Setup node in the Layout Manager to open the Layer Setup dialog box. A line type describes the layers used for a single trans-mission line, and the LPF file contains an entry for each line type. In this exam-ple, line types have been created for the RF signal lines, microstrip and stripline; and both surface and buried thin film resistors. Layer is the name of the model layer, Offset is the offset used for drawing the layer, and minWidth is used for checking design rule violations.

$LINE_TYPE_BEGIN"microstrip"! -> Layer offset minWidth flags"M12 (Microstrip)� 0 2e-005 0$LINE_TYPE_END

$LINE_TYPE_BEGIN"Stripline"! -> Layer offset minWidth flags"M4 (Stripline)� 0 2e-005 0$LINE_TYPE_END

$LINE_TYPE_BEGIN"Surface Resistor"! -> Layer offset minWidth flags"M12-1 (Resistor)� 0 2e-005 0$LINE_TYPE_END

$LINE_TYPE_BEGIN"Buried Resistor"! -> Layer offset minWidth flags"M4-1(Buried Resistor)"0 2e-005 0$LINE_TYPE_END

LPF file settings are reflected in the Layer Setup dialog box. Any changes in the *.LPF file display here.

A p p l i c a t i o n N o t e s 3

L T C C D E S I G N

LTCC Example

Figure 2. LTCC Drawing Layers

Figure 3. RFIC Drawing Layers



Figure 4. LTCC Layer Mapping

Figure 5. LTCC 3D Properties


L T C C D E S I G N

LTCC Example

Figure 6. LTCC EMSight Mapping

Creating Artwork CellsA subsystem design consists of different types of circuit elements such as a behavioral mixer model, data files for a filter, and device level nonlinear models. Each of these different elements require a physical implementation for the lay-out. Microwave Office uses artwork cells to represent the layout properties of a circuit element. Microstrip and stripline elements have default layout properties that are built into the software. The other circuit elements have layout cells that are either imported as standard CAD drawing cells, or created with the Micro-wave Office Artwork Cell Editor. (See the Microwave Office User Guide for more information about creating artwork cells.) The following figures show how the artwork cells are implemented.

1. The mixer package was drawn in the Artwork Cell Editor from a data sheet. The number of cell ports must match the number of subcircuit ports. Cell ports 2a and 2b represent the same port for simulation in a schematic, but require different physical representation in a layout. In this example, the art-work can only be assigned to a 5-port subcircuit.



Figure 7. Artwork Cell for a 5-Port Subcircuit

2. The RF low noise amplifier in this subsystem is implemented using S parameter data for simulation and an imported artwork cell for layout. The GDSII library �LNA900 IC� is imported and the artwork cell �LNA900 IC� is edited to include cell ports and bias lines, as shown in Figure 8.

Figure 8. LNA900IC with Cell Ports and Bias Lines Added

Cell Port 3

Cell Port 2a

Cell Port 1Cell Port 4

Cell Port 2b

Cell Port 5

Bias Lines

Cell Port 1

Cell Port 2


L T C C D E S I G N

LTCC Example

3. The buried and surface thin film resistor elements require separate artwork cells that fit the LTCC design guidelines. Parameterized layout cells are cre-ated using the Cell Stretcher in the Artwork Cell Editor. (See the Microwave Office User Guide for more information about stretching artwork cells.)

Figure 9. Buried and Surface Thin Film Resistor Artwork Cells

4. The remainder of the layout cells for capacitors, inductors, transistors, and the filter are created or imported, and then edited in the same manner. Many of the capacitors and inductors are from an XML library which auto-matically imports the proper artwork cell for a given element. (See the Microwave Office User Guide for more information about XML libraries.)

Creating Via Cells and Via ArraysVia holes are used for the following typical applications in LTCC:

� RF ground arrays - Ground arrays can separate signal paths on different layers (also called picket fence vias), or ground RF circuit elements.

� RF vias - RF vias transition the RF signal to different metal layers.

� Thermal arrays - Thermal arrays are used to extract the heat from an active device, and also act as electrical ground. The via pattern differs from the RF vias, as the vias are not staggered to maximize the heat transfer.

These via types typically have specific spacings and size restrictions depending on the process. The most efficient way to capture these specifications is to cre-ate artwork libraries for each via type. The GDSII drawing format in Microwave Office has a hierarchy that is very useful in via cell creation. LTCC requires the use of staggered vias-- the vias on alternating layers are offset to accommodate

Buried resistor

Surface resistor

Length stretcher

Width Stretcher



alignment issues during processing. The simplest way to accommodate these vias is to draw one via cell for each set of alternating layers. For example, if the via array connects all twelve layers, an odd cell, �vias odd 11_1�, with odd-num-bered via layers is created, and an even cell, �vias even 12_2�, with even-num-bered via layers is created. The odd and even via cells are placed in alternating patterns as shown in Figure 10. The result is a staggered via array as shown in Figure 11.

Figure 10. RF Via Array Artwork Cell Using Hierarchy

Figure 11. 3-D View of RF Via Array

The microstrip-to-stripline transition consists of both RF signal vias and �picket fence� grounding vias to isolate the RF signal as shown in Figure 12.

Artwork Cell�vias odd 11_1�

Artwork Cell�vias even 12_2�

Artwork cell�vias odd 11_1�

Artwork cell�vias even 12_2�


L T C C D E S I G N

LTCC Example

Figure 12. 3-D View of RF Microstrip-to-Stripline Transition

The thermal array vias have wider spacing because the vias are not staggered like RF vias. The via array for thermal vias includes all layers from via10 to via1. An artwork cell, �via 10_1� creates the via array. The thermal vias are typically placed under an active device as shown in Figure 13.

Figure 13. 3-D View of RFIC with Thermal Vias

RF signal vias

�picket fence�ground vias

RFIC chip

Artwork cell�via 10_1�



Creating a Model and Layout Cell for Buried SpiralsShrinking the layout requires using buried components such as spiral inductors. One of the issues for a buried spiral inductor is circuit modeling. Microwave Office has circuit models for microstrip spiral inductors only, so a model must be created for a buried or stripline spiral inductor. A combination of EM simu-lations and linear circuits is used to create a model that does not require EM simulations. The modeling process is as follows:

1. Create an EM simulation of the buried spiral. The complete EM buried spi-ral is shown in Figure 14.

Figure 14. 3-D View of the Complete EM Buried Spiral

2. Create an EM simulation of the airbridge for the spiral. The EM simulation is created as a reference measurement to model the airbridge with a linear schematic.

Figure 15. 3D View of Airbridge


L T C C D E S I G N

LTCC Example

3. Create a schematic to model the EM airbridge. The airbridge is modeled with a stripline pad connected to a via, connected to an offset stripline as shown in Figure 16.

Figure 16. Schematic for Linear Model of the Airbridge

The Smodel measurement is used to model the linear schematic to an EM struc-ture. It measures the difference between S parameters from two different sources. Optimize the linear schematic parameters to minimize the Smodel mea-surement.

Figure 17. SModel Measurement

S L IN

L=W =ID=

lpd m ilwp d m ilS L1

V IA

R HO =T=H =D =ID=

1 0.1 m il3.7 m il6 m i lV 1 S 1 L IN

A c c =L =

W =ID =

1 lb r m i lw br m ilTL 1

S S U B L

N a m e =R h o=

T =H 2 =H 1 =

T an d2 =T an d1 =

E r2 =E r1 =

S S UB L 1 1 0 .03 93 7 m i l1 8.5 m il1 1.1 m il0 .00 07 0 .00 07 5 .7 5 .7

S S U B

N am e=Ta nd =R ho =

T=B =

E r=

S S U B 1 0 1 0 .03 93 7 m il2 9.6 m il5 .7

V IA

R H O =T =H =D =

ID =

1 0 .1 m il3 .7 m il6 m ilV 2

S LIN

L =W =ID =

lp d m ilw pd m ilS L 3 P O R T

Z=P =

5 0 O hm1

P OR T

Z=P =

50 Oh m2

w br= 3

w pd =5

lbr=L -d elta L

lpd =5

de ltaL = 15

L= 3 4

0.1 1.1 2.1 3Frequency (GHz)

bridge smodel em

0

0.001

0.002

0.003SModel2[Em Airbridge]equivalent bridge with via



4. Combine the airbridge schematic model with a linear microstrip spiral ele-ment to model the complete EM buried spiral. The airbridge is a subcircuit that is connected to a microstrip spiral with no airbridge (MRINDNBR).

Figure 18. Schematic for Complete EM Buried Spiral

Optimize the linear buried spiral to match the EM buried spiral by varying the dielectric constant and height to minimize the Smodel measurement. The dielec-tric constant variable is ERnew, and the height variable is Hnew. A comparison of the S parameters for the EM and linear spiral is shown in Figure 19.

MSUB

Name=ErNom=

Tand=Rho=

T=H=

Er=

SUB1 5.7 0.0007 1.2 0.1 milHnew milERnew

MRINDNBR

S=W =LN=L3=L2=L1=

NS=ID=

3 mil3 mil10 milL1 milL1 milL1 mil15 MSP1

1 2

SUBCKT

NET=ID=

"equivalent bridge with via" S1 PORT

Z=P=

50 Ohm1

PORT

Z=P=

50 Ohm2

L1=68

ERnew=8.7

Hnew=17.6


L T C C D E S I G N

LTCC Example

.

Figure 19. S Parameter Comparison of EM Buried Spiral and Linear Spiral

To create the proper physical implementation of this model, an artwork cell is created for the Airbridge subcircuit as shown in Figure 20.

Figure 20. Airbridge Artwork Cell

The microstrip spiral has a default layout cell, and the airbridge subcircuit is assigned the airbridge artwork cell. The spiral layout is parameterized with the exception of the fixed airbridge. The layout cell is shown in Figure 21.

0 1.0

1.0

-1.0

10.0

10.0

-10.0

5.0

5.0

-5.0

2.0

2.0

-2.0

3.0

3.0

-3.0

4.0

4.0

-4.0

0.2

0.2

-0.2

0.4

0.4

-0.4

0.6

0.6

-0.6

0.8

0.8

-0.8

em spiral vs linear spiralSwp Max

3GHz

Swp Min0.1GHz

S[1,1]Copy 2 of EM Structure 1

S[1,1]stripline spiral with em bridge

1

2



Figure 21. Parameterized Spiral Layout Cell with Fixed Airbridge

Simulating RF Transitions with EMSightTransition between RF signal layers in LTCC requires models that are not readily available in traditional linear simulators. EM analysis is the preferred method for designing these transitions. Microwave Office provides a seamless link of EM simulations to linear and nonlinear schematics. The physical imple-mentation in EM can also be mapped to the layout so that there is no need to export geometries. To include both the EM simulation and layout in the com-plete receiver:

1. Create an EM structure with nine dielectric layers and one air layer. Layer 1 is the air layer above the dielectric. Layers 2-9 are the layers of 3.7 mil LTCC dielectric that are used for the via transition from microstrip to stripline. Layer 10 is the bottom layer of the stripline and is not stratified because there are no vias in this layer.


L T C C D E S I G N

LTCC Example

Figure 22. Ten-layer EM Structure

2. Map the EM structure to the layout in the Layer Setup section of the Lay-out Manager. The EM mapping maps metal layers and via layers to the schematic layout. The EM metal layers 2 - 10 are mapped to the LTCC metal layers M12 - M4. The EM via layers are mapped by selecting the Is Via column for every metal layer that has a via, as shown in Figure 24. EM layers do not have separate via layers; the vias are considered to extrude downward from a metal layer.

Figure 23. Mapping Metal Layers and Via Layers to the Schematic Layout

Layer 1Air

Layers 2-5MicrostripLayers 6-9Top StriplineLayer 10Bottom Stripline



3. The EM structure can now be placed in a schematic as a subcircuit, and the layout of the EM structure is included in the schematic layout.

Figure 24. Schematic Including EM Structure as Subcircuit

Figure 25. Schematic Layout Including EM Structure as Subcircuit

S CTRACE

R=L=

W =ID=

1 .5 m il6 .2 m il3 m ilTL25

MSTEP$ID= TL26

S CTRACE

R=L=

W =ID=

5 m il12.69 m il10 m ilTL27

SUBCKT

NET=ID=

"str ip line sp iral n10" S12

1 2

SUBCK T

NET=ID=

"Ustrip to str ip 90" S10


L T C C D E S I G N

LTCC Example

Assigning Artwork Cells and Line Types to Schematic Elements

A subsystem design consists of different types of circuit elements such as a behavioral mixer model, data files for a filter, and device level nonlinear models. Each of these different elements require a physical implementation for the lay-out. To complete the layout, all schematic elements must have the proper layout properties; artwork cells must be assigned to schematic elements.

The Mixer Package in this project is an example of a complex layout-to-sche-matic association. The other package assignments are more common and are discussed in the Microwave Office User Guide. The Mixer Package is assigned to the �Mixer Section� subcircuit. It requires five ports, while the mixer behavioral model has only three ports. The �Mixer Section� subcircuit is created to solve this problem.

Figure 26. Mixer Section Subcircuit

Ports 1 and 2 are isolated from the Mixer model by large resistors so that any-thing connected to those ports has no effect on the simulation. This technique is used to associate layout cells to schematic elements that have no simulation properties. In this case, Port 1 is a biasing network and Port 2 is RF ground. In Figure 27, the MLSC lines are added to create the proper physical implementa-tion of the Mixer. The MLSC elements are assigned one port RF ground ele-ment. Face properties are used to assign each ground to faces 2a and 2b of the Mixer Package. See the Microwave Office User Guide for more information about face properties.

RF IN IF OUT

LO

MIXER

PLO=LO2IF=RF2IF=

IP3_IN=P1DB_IN=GCONV=

ID=

-3 dBm-11 dB-11 dB-2 dBm-10 dBm5.5 dBMX1

RES

R=ID=

1e6 OhmR1

RES

R=ID=

1e6 OhmR2

PORT

Z=P=

50 Ohm3

PORT

Z=P=

50 Ohm1

PORT

Z=P=

50 Ohm2

PORT1

Pwr=Z=P=

-30 dBm50 Ohm5

PORTF

Pwr=Freq=

Z=P=

2 dBm0.998 GHz50 Ohm4



Figure 27. Mixer Section

Figure 28. Mixer Section Layout

Examples of schematic and layout association are shown in the following fig-ures.

MLSC

L=W =ID =

0 m il30 m ilTL1

MLSC

L=W =ID=

0 m i l30 m i lTL2

MTR ACE

M=BType =

L=W =ID=

0 3 30.83 m il15 m ilX1

MTRAC E

M=BType=

L=W =ID =

0 3 31.67 mi l15 m ilX2

MTR ACE

M=BTyp e=

L=W =ID=

0 3 175 m i l15 mi lX6

MTRAC E

M=BType=

L=W =ID =

0 3 30.8 3 m il15 m ilX8

1

2

3

4

5

SU BC KT

NET=ID =

"Mixer Sec tion" S3

�Emitter Gnd� artwork cell assigned to MLSC element


L T C C D E S I G N

LTCC Example

Figure 29. Linear Simulation of RFIC LNA with S Parameters

Figure 30. LNA RFIC Layout with RF and DC Connections.

MTAPER

L=W2=W1=ID=

70 mil5 milW@1 milMT1

MTAPER

L=W2=W1=ID=

50 mil5 milW@1 milMT2

1

2

SUBCKT

NET=ID=

"LNA900 IC" S1



Figure 31. Schematic of LO Buffer Amp in LTCC Process

Figure 32. Layout of LO Buffer Amp in LTCC Process

M SU B

Na me =Er N om =

Tan d=Rh o=

T=

H=Er =

SU B1 5. 7

0. 0007 1. 2 0. 1 m i l

14. 8 m il5. 7

M TR A CE

M =B Typ e=

L =W =I D =

0 2 1 5 mi l2 4 mi lX 1

SC TR A CE

R =L=

W =I D=

50 m il5 m il10 m ilTL 1

1

2

3

4

S CR O S$I D= S L1

SC TR A CE

R =

L=W =I D=

5 m il

17. 77 m i l10 m ilTL 2

SC TR AC E

R=L=

W =

ID =

50 m il39. 39 m il10 m il

TL3

SC TR AC E

R=L=

W =ID =

50 m il52. 34 m il10 m ilTL4

1

2

3

S TE E

W 3=

W 2=W 1=

I D =

1 0 mi l

W 5k m ilW 5k m ilS L2

S CT RA CE

R =L=

W =I D =

5 m i l59 .0 8 m i l3 m i lT L5

ML SC

L=W =ID =

0 m i l30 m ilTL6

M LS C

L =W =I D =

0 m i l3 0 m i lT L7

S CT RA C E

R =L =

W =I D =

5 m i l9 4. 78 m il

1 0 mi lT L8

C HI PC AP

ALP H=FR =

FQ =Q=C=ID =

-1 0. 23 GH z

0. 03 GH z779 1000 pFC1

M TR AC E

M =

B Type =L=

W =

I D =

0 . 6

2 22 .2 5 m i l10 m i l

X 2

M ST EP $I D= T L9

M TR AC E

M =B Typ e=

L =

W =I D =

0 2 2 5 m i l

1 20 m ilX 3

M TR AC E

M =B Typ e=

L =W =I D =

0 2

2 5 m i l1 20 m ilX 4

S CT RA CE

R =L=

W =I D =

1. 5 m il30 .0 3 m i l3 m i lT L11

1

2

3S TE E

W 3=W 2=W 1=

I D =

1 0 mi l3 m i l3 m i lS L3

SC TR AC E

R=

L=W =ID =

5 m i l

82. 35 m il10 m ilTL13

S CT RA CE

R =L=

W =I D =

1. 5 m il10 m i l3 m i lT L14

C H IP CA P

AL PH =FR =

FQ =Q =C =

I D=

- 1 0. 999 9 G H z

0. 15 G Hz376 .1 100 p FC 2

M T RA CE

M =

BT y pe=L=

W =ID =

0. 6

2 18. 17 m il10 m ilX6

M ST EP $I D= TL1 6

MT RA C E

M =

BT ype=L=

W =ID =

0

2 15 m il60 m ilX7

M TR AC E

M =

B Type =L=

W =I D=

0

2 15 m i l60 m i lX 8

M TR AC E

M =

B Typ e=L =

W =I D =

0 .6

2 1 3.7 1 mi l1 0 m i lX 9

M T RA CE

M=BTy pe=

L=W =ID =

0.6 2 10. 79 m il5 m i lX10

M LS C

L =W =

I D =

0 m i l3 0 mi l

T L17

M TR AC E

M =B Type =

L=W =I D=

0 . 6 2

15 7. 5 m i l10 m i lX 11

CH IP C AP

A LPH =F R=

F Q=Q =C =

I D=

- 1 0. 23 G H z

0. 03 G H z77 9 10 00 pFC 3

MS TE P$ID = TL1 8

M T RA CE

M=

BTyp e=L=

W =

ID =

0 .6

2 12. 8 mi l10 m il

X12

M TR AC E

M =

B Typ e=L =

W =I D =

0

2 2 5 m i l1 20 m ilX 13

M ST EP $I D= TL 19

M T RA CE

M=

BTy pe=L=

W =ID =

0

2 25 m il120 m ilX14

MT RA C E

M =

BT y pe=L=

W =ID =

0. 6

2 171 .1 m il10 m ilX1 5

S C TR AC E

R =L =

W =I D =

1 .5 m i l7 6. 87 m il

3 m i lT L20

S CT RA CE

R =L=

W =I D =

5 m i l28 1. 6 m i l10 m i lT L22

M ST EP $I D= TL 12

D C VS

V =I D =

3 VV 1

M TR A CE

M =B Typ e=

L =W =I D =

0 .6 2 3 2. 2 m i l2 4 mi lX 18

M S TE P$I D = T L15

1 2

3

M TE E$I D= T L21

C H IP CA P

AL PH =

FR =FQ =

Q =

C =I D=

- 1

0. 999 9 G H z0. 15 G Hz376 .1

100 p FC 4

M T RA CE

M=BTy pe=

L=W =ID =

0 2 15 m il60 m ilX17

SC TR AC E

R=L=

W =ID =

50 m il25 m il

10 m ilTL2 3

M TR AC E

M =

B Type =L=

W =

I D=

0. 6

2 41 .89 m i l24 m i l

X 20

VI A

RH O =T=H=D=

ID =

1.2 0.0 1 mi l29. 6 mi l6 m i lV2

12

3

M TEE

W 3 =W 2 =W 1 =

I D=

10 m i lW @ 2 m i lW @ 1 m i lTL 24

ML IN

L=W =ID =

15. 94 m il24 m ilX21

M LI N

L =W =I D =

1 5 m i l6 0 m i lX 19

MT RA C E

M =BT ype=

L=W =ID =

0. 6 2 119 .5 m il5 m ilX5

SC TR AC E

R=L=

W =

ID =

1. 5 m i l6. 2 m i l3 mi l

TL2 5

M S TE P$I D = T L26

SC TR AC E

R=L=

W =

ID =

5 mi l12. 69 m il10 m il

TL2 7

MT RA C E

M =

BT y pe=L=

W =I D=

0. 6

2 57. 12 m il24 m ilX1 6

M TR AC E

M =B Ty p e=

L =W =I D =

0 .6 2 7 0 mi l2 4 mi lX 22

S SU B

N am e=T and=

R ho=T =B =

E r=

S SU B1 0

1 0. 03 937 m il29 .6 m i l

5. 7

C

B

E

1

2

3

S U BC KT

NE T=ID =

" BFP 181 " S1

SU BC K T

N ET =I D=

" st ri pl ine sp ir al n 18" S 9

SU BC KT

N ET=

I D=

" st ri p l ine sp ir al n1 0"

S1 2

SU BC K T

N ET =I D=

" st ri pl ine sp ir al n 15" S 6

S UB CK T

N E T=I D =

" R esi st or 10 0" S 7

SU BC K T

N ET =

I D=

" R esis tor 22k"

S 4

S U BC KT

NE T=

ID =

" Res ist or 680"

S3

12

SU B CK T

N ET =I D=

" U str i p to st r ip 90 " S 8

1

2

S UB CK T

NE T=ID =

"U s t r ip t o s tr ip 9 0" S13

12

S UB CK T

N E T=I D =

" U st ri p to s t r ip t hr u" S 2

1 2

S UB C KT

NE T=ID =

"U st r ip t o str i p 9 0" S11

12

SU BC KT

N ET=I D=

" Us tr ip t o st ri p 90" S1 6

1 2

S UB CK T

N ET =I D =

" U s t ri p to st r ip 90 " S 10

12

S U BC KT

NE T=ID =

" Ust r ip t o str i p t hr u" S15

PO R T

Z =P =

5 0 O hm2

PO R T1

P w r=Z =P =

0 d Bm5 0 Oh m1

L1=6 8


L T C C D E S I G N

LTCC Example

The proper line types are assigned to the microstrip and stripline elements by selecting the element in the layout, right-clicking and choosing Shape Proper-ties.

Figure 33. Schematic for Microstrip-to-Stripline Transition with Line Types

Figure 34. Layout of Microstrip-to-Stripline Transitions with Line Types.

Routing Trace Lines for InterconnectionsOne of the most important steps in the layout of LTCC is the routing of the lines that connect different circuit elements. This routing is critical in compact-ing the layout. This step in the physical implementation of LTCC is difficult because it requires thought in three dimensions. Both microstrip and stripline traces must be routed to minimize the footprint of the layout while maintaining the integrity of the RF signal. Microwave Office has the following unique fea-tures to help route trace lines efficiently:

1. Trace elements are RF lines that can be routed in layout while retaining the correct lengths and bend information for simulation. The microstrip ele-

MTRACE

M=BType=

L=W =ID=

0 2 15 mil24 milX1

SCTRACE

R=L=

W =ID=

50 mil5 mil10 milTL1

12

SUBCKT

NET=ID=

"Ustrip to strip thru" S2

Microstripline type

Striplineline type



ment is MTRACE, and the stripline element is STRACE. These elements, along with special functions in layout, make line routing simple in Micro-wave Office. The following example illustrates the functionality of trace routing in the LTCC layout.

� In this example the layout has a closed loop so that one line must be precisely routed to complete the loop. Figure 35 displays the schematic and layout.

Figure 35. Schematic and Closed-Loop Layout with MTRACE Element

� The best way to route this line is to first clear the Snap to adjacent check box on the unconnected face, as shown in Figure 36.

Figure 36. Cell Options to Turn Off Snap to Adjacent

MT R A C E

M =B Ty p e =

L =W =ID =

0 2 1 5 m i l2 4 m i lX 1

S C TR AC E

R=L=

W =ID =

50 m il5 m il10 m ilTL 1

1

2

3

4

SC R OS $ID= S L 1

S CTR AC E

R =L =

W =ID =

5 0 m il3 9 .3 9 mi l1 0 m ilTL 3

M L S C

L =W =ID=

0 m il3 0 m ilTL 6

M L S C

L =W =ID=

0 m il3 0 mi lTL 7

M T R ACE

M =B Ty pe=

L =W =ID =

0 .6 2 1 6 8 .3 m il1 0 m ilX 1 1

C HIP CA P

A L PH =FR=FQ =

Q=C=

ID =

-1 0 .9 9 9 9 G H z0 .1 5 GH z3 7 6.1 1 0 0 p FC4

MT RAC E

M =B Ty p e =

L =W =ID =

0 2 1 5 m i l6 0 m i lX 1 7

S CTR AC E

R =L =

W =ID =

5 0 m il2 5 m il1 0 m ilTL 2 3

MT RA C E

M =B Ty p e =

L =W =ID =

0 .6 2 4 1 .8 9 m il2 4 m i lX 2 0

V IA

R H O=T =H =D =

ID =

1 .2 0 .0 1 m i l2 9 .6 m i l6 m i lV 2

12

3

M TE E

W 3 =W 2 =W 1 =ID =

10 m i lW @ 2 m i lW @ 1 m i lT L2 4

M LIN

L =W =ID =

1 5 .9 4 m il2 4 m i lX 2 1

M L IN

L=W =ID =

15 m i l60 m i lX1 9

C

B

E

1

2

3

S U BCK T

N ET =ID =

" B FP 1 81 " S 1

S UB C K T

NE T=ID =

"R es isto r 6 8 0 " S 3

1

2

S UB C K T

NE T=ID =

" Ustr ip to s tri p 90" S 1 3

12

SU B C K T

N E T=ID =

" U str ip to s trip thr u " S 2

MTRACE Element

Clear this checkbox


L T C C D E S I G N

LTCC Example

� The MTRACE is then routed with mouse clicks as show in Figure 37. (See the Microwave Office User Guide for more information about trace routing.)

Figure 37. Routing the MTRACE with mouse clicks.

� Select Snap to fit on the toolbar to finish the routing and complete the loop.

� The loop is complete and the faces of the MTRACE are connected properly. The final layout is shown in Figure 38.

Figure 38. Final Layout of Routed MTRACE

2. The 3D view is critical in helping to route the lines in the LTCC layout because it can identify any interference issues in the routing of a line.



� The 2D view of this section of the layout shows no potential interference issues. The stripline trace passes under the capacitor located on the same layer as the microstrip lines.

Figure 39. 2D View of Layout Shows No Interference

� The 3D view, however, shows a via array for ground that is interfering with the stripline trace.

Figure 40. 3D View Showing Via Array and Stripline Trace Conflict

� The hidden via array is now moved to correct the interference problem.


L T C C D E S I G N

LTCC Example

Figure 41. 3D View of Corrected Layout Showing No Interferences

Placing Via Fences and Via ArraysVia fences and via arrays are necessary to complete the layout. Via fences isolate RF signals and provide grounding structures for the microstrip-to-stripline tran-sitions. Via arrays are used to connect ground planes to ensure signal integrity. The fences and ground arrays have no simulation properties and are imple-mented as artwork cells which are placed directly onto the top level layout.



Figure 42. 2D View of the Complete Layout of the Receiver

Exporting Gerber and Drill FilesCommon file formats for LTCC manufacturers are Gerber and NC drill files. Gerber files are used to generate the masks for the metallization, and NC drill files are used to drill vias into the LTCC green tape. Microwave Office can out-put both file formats. There is typically one Gerber file for each metal layer and one drill file for every via layer. The following Visual Basic scripts written in the Microwave Office scripting engine are used to create the set of Gerber and drill files necessary for manufacturing.

1. The �Drill file� script creates a drill file for a specified via layer. To run the script, expand the Scripting node in the Project Browser. In the Script

Via Array

Via FenceTransition Gnd

Via FenceRF isolation


L T C C D E S I G N

LTCC Example

(project.emp) node, expand the Code Modules node. Double-click on the Drill file script to open a scripting window environment.

Figure 43. Drill File Scripting Window

� To run the script, click Run Sub in the toolbar. The script prompts you for the layout, via layer, units, and file name. The following shows the final drill file output for the via12 layer.

M48M72,LZT01C0.006%T01X-001757Y-000663X-001957Y-000663X-001757Y-000463X-001957Y-000463X-001857Y-000563X-001047Y-000464X-000847Y-000464X-001047Y-000664X-000847Y-000664X-000947Y-000564X000050Y-002788X000050Y-002988



X-000150Y-002788X-000150Y-002988

2. The �Export Gerber Files� script creates a Gerber file for every layer spec-ified in a chosen export layer mapping. Run the script, then select the layout and a Gerber mapping. The script generates a directory named �Gerber files� in the project directory, and creates a Gerber file for every layer in the layout. The Gerber files for this example are shown in Figure 44 and Figure 45.

Figure 44. Gerber Files Created for Every Layout Layer

Figure 45. Gerber Files in a Gerber Viewer


L T C C D E S I G N

Design Kits

DESIGN KITS

The �receiver ltcc v5 NEW.emp� project is based upon the capabilities in Microwave Office v5.50, and created without the use of a predefined design kit. A design kit would greatly simplify the design process by providing the follow-ing features:

� line definitions and models for signal lines on different layers

� parameterized models for buried and surface inductors, capacitors, and resistors

� library elements for SMT components and IC chips including data and layout

� design rule checking for the complete layout (see the Microwave Office User Guide for more information).

Design kit development requires the input of the designer, as LTCC designs provide maximum flexibility in physical implementation. Models for LTCC ele-ments must be verified with measured data, and guidelines developed for proper usage. The physical implementation of a circuit will vary among designers, how-ever common design methodologies must be defined to properly develop a use-ful design kit. A design kit provides maximum flexibility with correct models and design procedures to ensure accurate simulations. A simple example of a design kit follows.

The library elements are organized using XML (see the Microwave Office User Guide for more information on XML). The XML data includes the name, model type, description, and layout cell. In this example, the library consists of a variety of different model types and layout cells. The mixer is implemented with an AWR schematic element and a fixed artwork cell. The spirals are developed using an AWR schematic that is extracted from an EM simulation; the layout cell is a fixed artwork cell. The thin film resistors are implemented with AWR mod-els, and the layout consists of parameterized artwork cells that were created using the Cell Stretcher in the Artwork Cell Editor. The RF transitions are S parameter data files taken from EM simulations. The layout for the transitions is created using EM Mapping and the Artwork Cell Editor. The following are sam-ples of the XML text used to create the libraries:


L T C C D E S I G NDesign Kits

Top Level (AWR_LTCC.xml): <FOLDER Name="AWR LTCC Library parts">

<FILE Name="Shortcuts">..\XML\Shortcuts.xml</FILE>

<FILE Name="Vias and Pads">..\XML\ViasAndPads.xml</FILE>

<FILE Name="Res">..\XML\Res.xml</FILE>

<FILE Name="Spirals">..\XML\Spiral.xml</FILE>

<FILE Name="RF Transitions">..\XML\Transitions.xml</FILE>

<FILE Name="Active Devices">..\XML\Devices.xml</FILE>

</FOLDER>

Active Devices (Devices.xml):<COMPONENT Name="MIXER">

<MODEL>SUBCKT</MODEL>

<DESC>Mixer CMY91</DESC>

<SYMBOL>RCVRS_1_4@sys_block.syf</SYMBOL>

<CELL>Mixer Package@..\Library\Mixer.gds</CELL>

<DATA DataType="awrschematic" Inline="no">

..\Library\Schematics\mixer section.sch

</DATA>

</COMPONENT>

</XML_COMPONENT_DATA>

Res:<COMPONENT Name="Bur_100_TFR">

<MODEL>TFR</MODEL>

<DESC>Buried Thin Film Resistor 100 ohms square</DESC>

<SYMBOL>[email protected]</SYMBOL>

<CELL>Buried TFR@..\Library\Resistors.gds</CELL>

<DATA DataType="awrmodel" Inline="yes">

<PARAM Name="ID">Bur_TFR100_</PARAM>

<PARAM Name="W">2.54e-4</PARAM>

<PARAM Name="L">2.54e-3</PARAM>

<PARAM Name="Rs">100</PARAM>

<PARAM Name="F">0</PARAM>

</DATA>

</COMPONENT>


L T C C D E S I G N

Design Kits

RF Transitions (Transitions.xml):<COMPONENT Name="USTOS">

<MODEL>SUBCKT</MODEL>

<DESC>RF transition microstrip to stripline thru</DESC>

<SYMBOL>viatrans@awr_ltcc.syf</SYMBOL>

<CELL>M12to M4_thru@..\Library\Rf transitions.gds</CELL>

<DATA DataType="sparameter" Inline="no">

../Library/Spar/Ustrip to strip thru.s2p

</DATA>

</COMPONENT>

The XML libraries allow you to drag and drop elements into a schematic. The associated schematics and layout cells for each element are automatically imported into the project. The schematic in Figure 46 was created from the XML library.

Figure 46. Schematic with XML Library Elements

The layer process file along with the XML libraries enables the layout to display dynamically in 2D and 3D views.

MTRACE

M=BType=

L=W=ID=

0 2 51.6 m il24 milX1

MTRACE

M=BType=

L=W =ID=

0 3 96.7 mil24 m ilX2

MTRACE

M=BType=

L=W =ID=

0 2 80.1 mil24 m ilX3

MLSC

L=W =ID=

0 mil10 milTL1

MLSC

L=W =ID=

0 mil10 milTL2

SLIN

L=W=ID=

24.9 m il3 milSL1

SLIN

L=W =ID=

24.9 mil3 milSL2

12

3

STEE$ID= SL3

SLIN

L=W=ID=

20 mil20 milSL4

SLIN

L=W =ID=

13.4 mil3 milSL5

VIA

RHO=T=H=D=ID=

1 0.1 mil29.5984 m il6 m ilV1

MTRACE

M=BType=

L=W=ID=

0 3 100 mil24 milX4

TFR

F=RS=

L=W =ID=

0 GHz100 100 m il10 m ilBur_TFR100_1

SLIN

L=W=ID=

20 mil20 milSL6

SSUB

Name=Tand=Rho=

T=B=

Er=

SSUB1 0.0007 1 0.15748 m il29.6063 m il5.7

M SUB

Nam e=ErNom=

Tand=Rho=

T=H=

Er=

SUB1 5.7 0.0007 1 0.15748 m il14.8031 m il5.7

R D

IQ

1 2

3

45

SUBCKT

NET=ID=

"mixer section" S1

12

SUBCKT

NET=ID=

"Ustrip to strip thru" S2

SUBCKT

NET=ID=

"stripline spiral n18" S3

1

2

SUBCKT

NET=ID=

"Ustrip to strip 90" S4


L T C C D E S I G NDesign Kits

Figure 47. 2D View of Schematic with XML Library Elements

Figure 48. 3D View of Schematic with XML Library Elements


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