reliability enhancement via sleep transistors
DESCRIPTION
Reliability Enhancement via Sleep Transistors. Frank Sill Torres + , Claas Cornelius*, Dirk Timmermann* + Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil - PowerPoint PPT PresentationTRANSCRIPT
Reliability Enhancement via Sleep Transistors
Frank Sill Torres+, Claas Cornelius*, Dirk Timmermann*
+ Department of Electronic Engineering, Federal University of
Minas Gerais, Belo Horizonte, Brazil
* Inst. of Applied Microelectronics and Computer Engineering,
University of Rostock, Germany
2Sill Torres et al.– Reliability w/ Sleep Transistors
Focus / Main ideas
1. Approach for extension of expected lifetime
2. Application of simulation environment for
MTTF estimation
3Sill Torres et al.– Reliability w/ Sleep Transistors
Motivation
Preliminaries
Reliability Enhancement via Sleep Transistors
Simulation Environment
Results
Conclusion
Outline
4Sill Torres et al.– Reliability w/ Sleep Transistors
Probability for failures increases due to: Increasing transistor count Shrinking technology
MotivationTechnology Development
2002 2004 2006 2008 20100
300
600
900
1200
nm
20 nm
40 nm
60 nm
80 nm
100 nm
120 nm
140 nm
130 nm
90 nm 65 nm 45 nm
32 nm
Ano
Tec
no
log
ia
2002 2004 2006 2008 20100
300
600
900
1200
Year
# T
ran
sist
ors
(M
ill.
)
Wolfdale410 Mil.
Northwood55 Mil.
Prescott125 Mil.
Yonah151 Mil.
Gulftown1.170 Mil.
Wolfdale410 Mil.
Tecn
olo
gy
5Sill Torres et al.– Reliability w/ Sleep Transistors
MotivationError classification
Error
PermanentTemporarySoft errors, Voltage drop, Coupling, …
Reduced PerformanceProcess variations, Electro-migration, Oxide wearout, NBTI, ...
MalfunctionElectromigration, Oxide breakdown ...
6Sill Torres et al.– Reliability w/ Sleep Transistors
Preliminaries
Very well-known and effective
approach for leakage
reduction
Insertion of sleep transistors
(mostly with high-threshold
voltage) between logic module
and supply
Disconnection from supply
during standby
Power-Gating with Sleep Transistors
M. Powell, et al., Proc. ISLPED, 2000. A. Ramalingam, et al., Proc. ASP-DAC, 2005.
Sleep
Sleep
virtual GND
Logic block
virtual VDD
High-Vth
7Sill Torres et al.– Reliability w/ Sleep Transistors
Electromigration (EM)– Performance reduction and errors
– Depending on currents and temperature
Negative Bias Temperature Instability (NBTI)– Performance reduction
– Depending on voltage level and temperature
Time Dependent Dielectric Breakdown (TDDB) – Performance reduction and errors
– Depending on voltage level and temperature
PreliminariesTime Dependent Failure Mechanisms
Increase of lifetime through reduction of supply voltage and activity
8Sill Torres et al.– Reliability w/ Sleep Transistors
SLEEP
Basic idea: Reduction of degradation via module deactivation
Problem: What to do at run-time?
Reliability Enhancement via Sleep TransistorsConcept and Realization
ModuleModule
Module 1Instance 2
Module 1Instance 1
Module 2
MUX
tlife-new ≈ tlife-old + toff
tlife-system = tlife-module
≈ tlife-old + toff
≈ 2* tlife-old + tsleep
9Sill Torres et al.– Reliability w/ Sleep Transistors
Lifetime
– Increase by more than factor 2 (not linear relation between
effective voltage and failure mechanisms)
Area
– Increase by slightly more than factor 2
– Ca. 50 % less than Triple Modular Redundancy (TMR)
Power dissipation
– Slight increase of dynamic power dissipation
– Increase of leakage by ca. factor 2
Delay
– Slight increase through multiplexer delays
Reliability Enhancement via Sleep TransistorsExpectations
10Sill Torres et al.– Reliability w/ Sleep Transistors
Application
– Limited improvements for devices with long standby times
(mobiles, home PCs)
– High improvements for high availability applications (server,
aerospace equipment, mobile communication nodes)
Multiplexer
– Problem: no deactivation of multiplexer
– Solution: use of transmission gates (less vulnerable)
Control signals (for sleep transistor, multiplexer)
– Logic for control signal generation must be reliable too
– Hence: reliable implementation (HighTox, wire widening, …)
– More research required
Reliability Enhancement via Sleep TransistorsComments
11Sill Torres et al.– Reliability w/ Sleep Transistors
Desired: Simulative estimation of average time until first failure (also
known as Mean Time To Failure – MTTF)
Solution:
– Application of voltage controlled variable elements and
parameters for failure modeling (xSpice, VerilogA, …)
– Linear increase/decrease of control voltage at simulation time
Example: HSPICE model of transistor with TDDB and varying width
Simulation Environment
V0 Vref 0 DC 1V1 Vctrl 0 PULSE 1e12 0 0 1E-2 1E-9 1E1 2E1M0 D G N1 0 nmos W='1e-7 * V(Vctrl)/V(Vref)'M1 N1 G S 0 nmos W='1e-7 * V(Vctrl)/V(Vref)'G1 G N1 VCR Vctrl 0 10
12Sill Torres et al.– Reliability w/ Sleep Transistors
ResultsMean Time To Failure (MTTF)
(BPTM 22nm, 100 samples, TDDB and EM modeling, basic MTTF of 300 clock cycles, relaxed timing, w/o temperature consideration)
2.2
13Sill Torres et al.– Reliability w/ Sleep Transistors
Results Delay / Power / Area
Average values: Delay: + 7 %, Power: + 5 %, Area: + 110 %
14Sill Torres et al.– Reliability w/ Sleep Transistors
Conclusion
Progressing susceptibility of current technologies against severe
failure mechanisms
Extension of expected lifetime by alternating (de-)activation of
redundant blocks via sleep transistors
Environment for simulation of time-dependent degradation of design
components
Increase of MTTF by more than factor 2 through proposed
approach
Factor 1.2 for relation of average increase of MTTF and area
Future tasks:
– Application of selective redundancy techniques
– Merging with approaches on system level
– Analysis of control logic
16Sill Torres et al.– Reliability w/ Sleep Transistors
MotivationTime-Dependent Dielectric Breakdown (TDDB)
Tunneling currents
Wear out of gate oxide
Creation of conducting path
between Gate and Substrate,
Drain, Source
Depending on electrical field over
gate oxide, temperature (exp.),
and gate oxide thickness (exp.)
Also: abrupt damage due to
extreme overvoltage (e.g. Electro-
Static Discharge)Source: Pey&Tung
Source: Pey&Tung
17Sill Torres et al.– Reliability w/ Sleep Transistors
Reliability Enhancement via Sleep TransistorsRealization
18Sill Torres et al.– Reliability w/ Sleep Transistors
Reliability Enhancement via Sleep TransistorsBlocks / Requirements
Sleep 1
Sleep 2
MUX-ctrl
timet1 t2 t3t0
19Sill Torres et al.– Reliability w/ Sleep Transistors
Simulation EnvironmentOverview
20Sill Torres et al.– Reliability w/ Sleep Transistors
Simulation EnvironmentError Modeling
Source Drain
Gate
VA
V1 Vctrl 0 PULSE 1e12 0 0 1E-2 1E-9 1E1 2E1M0 D G N1 0 nmosM1 N1 G N1 0 nmosX1 G N1 Vctrl resistor
module resistor(p, n, Ve); electrical p, n, Ve; analog begin V(p,n) <+ V(Ve) *I(p, n); endendmodule
HSp
ice
Veril
ogA