Institut fur Integrierte Systeme

Integrated Systems Laboratory

Analog Integrated CircuitsExercise 6: Layout

Danny Luu ETZ J61, Xu Han ETZ J64.2

Hand out: 05.12.2014

The exercise takes place in room ETZ D61.1 on 5th and 12th of December. The exercisestarts at 13:15 and ends at 15:00.

1 Introduction

From Exercise 2 to Exercise 5, we have calculated different circuits, and simulations are used to guaran-tee the specifications. Now, the designers of Analog IC must convert the schematic into a physical chip.For that, a so-called layout must be generated, which will beused as photolithography masks during thefabrication of the chips.

In this exercise, a finished layout of a simple amplifier (OTA)is provided, and it will be analyzed andcompared with the associated schematic. For the layout, certain geometrical rules (Design Rules) mustbe satisfied, e.g. minimum width and minimum spacing. A program (DRC=Design Rule Check) canbe used to check the Design Rules and announce possible errors. Furthermore, it must be guaranteedthat the schematic and the layout represent the same circuit. In order to do this, the layout should beextracted firstly. A program (Extractor) looks into the layout to extract electrical devices (transistors, re-sistors, capacitors) and generate a netlist from it. Secondly, with a further program (LVS=Layout VersusSchematic) this netlist is compared with the netlist of the schematic and is examined for agreement.

2 CMOS Process

In this exercise, a 0.35m CMOS process with four metal layers and two polysilicon layers is used.The minimum channel length of the transistors is 0.35m. With four metal layers low impedanceconnections can be implemented. Usually, the polysilicon is used only for the gates of transistors,since its resistance is much higher than the metals. As here in the special case of two polysilicon layers,the second layer is used for poly-poly capacitors only.

Figure 1 shows the cross section of an NMOS (left) and a PMOS transistor (right). All transistors arefabricated in a weakly doped p-type substrate (p-), which also forms the bulk connections of all NMOStransistors. Drain and source of the NMOS transistor consist of two heavily doped n-type (n+) regions.

Figure 1: The symbol, cross section and layout of MOS transistors

The channel is under the Polysilicon gate. In addition, contacts must be etched in the isolating oxide toconnect diffusions with metals.

Underneath the cross section, the layout of the corresponding transistors is shown (top view). It consistsof the drain and source diffusions (light gray), the polysilicon gate (dark gray), the contacts (black)and the metal leads for drain and source (transparency). In contrast to the NMOS transistor, the PMOStransistor lies additionally in a weakly doped n-type well (n-), while the drain and source diffusions areheavily doped (p+).

Because of the weakly doping, the p-substrate conduction ispoor. So everywhere in the substrate, it isnecessary to add many substrate contacts and connect them with metal directly. The same applies to then-well, too. In addition, consider that in the cross sectionof Figure 1 not only MOS transistors, but alsosome unwanted diodes (pn junction) exist. These diodes mustbe reversed biased to prevent them from

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conducting. Therefore, the substrate is always connected to the lowest potential of the circuit, and then-wells are usually connected to the highest potential.

Besides MOS transistors, resistors and capacitors can alsobe integrated. In this exercise, we will con-centrate on MOS transistors only. Bipolar transistor (BJT)needs further process steps and thus alsofurther masks, so it cannot be integrated in an ordinary CMOSprocess.

Remark: Although a MOS transistor consists of separate diffusion areas for drain and source, only alarge diffusion is drawn in the layout, which covers the channel together with drain and source. Thereason for this lies in the fabrication process. In a modern CMOS process, the polysilicon gates isdeposited firstly, and then the wafer is exposed to a dopant source. So, the gate acts as barrier andprevents the channel from doping. The advantage of this procedure is that the channel is always exactlyunder the gate, even if the mask is slightly shifted.

3 Design Rules

As was already mentioned in the preceding section, the minimum channel length of the transistors isequal to 0.35m. This length is determined by the chip manufactory (wafer foundry). With shorterchannel length, more transistors can be integrated, which is favorable for very large circuits (micro-processors, memorys, etc.) and high speed circuits.

In Table 1 the minimum widths and spacings within the same mask are listed for all masks. The dataare all in micrometers. Figure 2 contains some geometrical rules for the masks among themselves.

Mask Abbreviation Minimum Width Minimum Spacingsn-Well NTUB 1.7 1Diffusion DIFF 0.3 0.6n+ Diffusion NPLUS 0.6 0.6p+ Diffusion PPLUS 0.6 0.6Polysilicon 1 POLY1 0.35 0.45Polysilicon 2 POLY2 0.65 0.5Contact CONT 0.4 0.4Metal 1 MET1 0.5 0.45Via 1 VIA1 0.5 0.45Metal 2 MET2 0.6 0.5Via 2 VIA2 0.5 0.45Metal 3 MET3 0.6 0.6Via 3 VIA3 0.5 0.45Metal 4 MET4 2.5 2

Table 1: Minimum widths and spacings of the masks

For n+ and p+ diffusion, three masks are needed. The n+ diffusion must be drawn with the masksDIFF and NPLUS, and the p+ diffusion must be drawn with DIFFand PPLUS. Three masks for onlytwo diffusion types may be strange, however, in most CMOS processes this is a normal case.

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Figure 2: Additional design rules for transistors, contacts, metals and vias

Mask Via 1 defines connections between Metal 1 and Metal 2, andVia 2 defines connections betweenMetal 2 and Metal 3.

4 Layout Editor

In this section the layout editor will be introduced. On the basis of a finished layout, simple operations,e.g., zoom in/out and fading in/out different layers will bepresented.

In a terminal, enter the following commands:

cp -r ~aic 00/uebung6 .cd uebung6icdesign&

Start theDesign Framework II and open the library manager. If you dont see the libraryueb6 in yourlibrary manager, contact an assistant. Open the thelayout view of the cellota from the libraryueb6.This will open a window, which is shown in Figure 3, containing the layout of the circuit and the layerselection window (LSW) on the left.

Possibly, in the layout window, not all hierarchy levels aredisplayed. In order to display these levels,open the display option form with the commandOptions.Display... and modify theStop valueof Display Levels from 0 to 20. Alternatively, useShift + f and Ctrl + f to toggle between showingall hierarchy levels or top level only.

The LSW may include some layers (masks) which are not needed at all. From the LSW dropdownmenu (see Figure 3) selectLayer Set.Import... to import the fileueb6Layers.layerSet. Now,the LSW contains only the layers listed in the Table 1 and the pin layers. With the help of the LSW,

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Figure 3: Layout view of the circuit with layer selection window (LSW).

arbitrary layers in the layout window can be made visible or invisible. In the LSW, click the layerPOLY1with the left mouse button. Now it is dark bordered, which means thatPOLY1 is the active layer (if wedraw something now, then this would be inPOLY1). When you click theNV (None Visible) button, thebackground of all layers except the active layer is grayed inthe LSW. The inactive layers are faded outin the layout window and onlyPOLY1 is visible. In the LSW, with the left mouse button, selected layerscan be made visible again. Try this for some layers. Click theAV (All Visible) button, all layers becomevisible again.

Zooming the layout view works similar as in the schematic view:Zoom In/Out: mouse wheelZoom In: Draw a rectangle with the right mouse button pressedX-Axis Scroll: Shift + mouse wheel

Y-Axis Scroll: Ctrl + mouse wheel

Fit all: f

You can arbitrarily detail the editing layout. Often, it is necessary to know the exact dimensions. Hereexists a useful commandTools.Create Ruler k to measure dimensions in the layout window.Use Shift + k to clear all rulers. The layout editor also provides a multiplicity of further functions. Forexample, you can test the function of the arrow keys in the layout window.

With the commands described above, the problems of the following section can be solved.

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5 Layout Analysis

In this section a finished layout is to be analyzed and be compared with the schematic in Figure 4. Usethe commands from the preceding section (zoom in/out, rulerand layer fade in/out).

Solve the following problems and annotate the results in thelayout of Figure 4.

Problems:

1. Find all transistors (Hint: Crossing of the layerPOLY1 and the layerDIFF forms a transistor)

2. Differentiate the NMOS transistors from the PMOS transistors (Hint: PMOS transistors lie in an-well)

3. Determine the sizes of all transistors (W/L)

4. Compare the found W/L with the schematic. Obviously, the layout has more transistors than theschematic. Why is that possible? (Hint: A transistor can consist of several fingers in the layout).

5. Assign all transistors in the layout to the transistors inthe schematic. Use the numbering used inthe schematic (M0, M1, M2, . . . )

6. Give the number of fingers for all transistors (you can use the table in Figure 4)

7. The geometrical structure of the differential pair M1, M2is called common centroid. Consideryourself, why such an arrangement is favorable for the offset of OTAs.

8. The bulk of the NMOS transistors is the p-substrate and must be connected to the lowest potential,thus to VSS (why?). Find the substrate contacts. Why do the substrate contacts lie in the proximityof drain and source of the transistors if possible?

9. The bulk of the PMOS transistors is the n-well. It must be connected to a high potential (why?).Find the n-well contacts. The n-well contacts lie in the proximity of drain and source, too.

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Figure 4: Schematic and layout of the OTA

6 Layout Drawing

In the previous section, a finished layout was analyzed. Now,you will draw your own layout for the sameschematic (Figure 4). In order to simplify the layout, common centroid is not used for the differentialpair, and the W/L of the transistors remains the same. M1, M2 and M0 are to exhibit four fingers,M3M6 and M9 two fingers and M7, M8 one finger.

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Create a new layout in the libraryueb6, with the cell namemyota and the typelayout. Firstly, youshall draw the transistors. Fortunately, the software saves a large part of work we need to do. Thetransistors can be generated withCreate.Instance... i . Browse for the desired component.The MOS transistors are in the libraryPRIMLIB. The cell name isnmos4 and pmos4, and the viewname islayout. Enter the width, length and number of fingers (number of gates). With the left mousebutton, the transistor can be placed in any desired location.

Generate all transistors with correct W/L and the indicatednumber of fingers. You may want to rotatecertain transistors. Select the transistor and open the Properties withEdit.Basic.Propertiesq . In the Attribute tab, you can change the rotation angle of the instance and in the Parameter tab,

you can modify the transistor dimensions. In addition, the selected transistors can be deleted withEdit.Delete Del .

After you placed all transistors, you can store your layout with File.Save.

The transistors must be electrically connected now. For this, layers Metal1, Metal2, and Metal3 shouldbe used. Metal4 is a thick metal and not intended for local interconnections. In the LSW, select Metal1,Metal2 or Metal3 (with the left mouse button, the selected layer will be dark bordered), and draw arectangle withCreate.Shape.Rectangle r . A more comfortable alternative for interconnectionsis to use the so-called PathCreate.Shape.Path p . It does not matter for the layout whetherrectangles or paths are drawn.

In order to connect the different transistors, you also needto place contacts and vias. Poly1-gates anddiffusion areas must be connected with Metal1 by contacts and the different metals are connected byvias. As in the case of transistors, contacts and vias can also be generated automatically. You can usethe commandCreate.Via... o . There are several different contact and via types.P1 C can beused to connect Poly1 and Metal1,PD C is used to connect p+ diffusion and Metal1,ND C is used toconnect n+ diffusion and Metal1,VIA1 C is used to connect Metal1 and Metal2, andVIA2 C is used toconnect Metal2 and Metal3.

Finally you need to specify the input and output ports where the circuit will be connected to the sur-rounding environment. The way to do this depends on the toolkit being used. In the setup used here, itis sufficient to place labels using thePIN layer. For example if a wire on Metal3 connects to the outputof the circuit, you have to create a label byCreate.Label... l , give it a name, select the PINlayer with subtype Metal3 (PIN|M3) and place it on top of the wire. Make sure that the crosshair of thelabel is inside the metal area. There is no option to specify whether a label represents an input or outputport. Place labels in the layout view with exactly the same names as the pins in the schematic view ofthe circuit.

When drawing the layout, pay attention not to violate the design rules. Accomplish regularly design rulecheck and you can correct the errors promptly. The checker can be started withAssura.Run DRC.Fill in the DRC form in accordance with Figure 5 (Notice the Switch Names!). PressOK to start theDRC and confirm if there are windows asking about overwritingprevious results. Wait until the DRCrun has completed successfully (if not, ask an assistant) and have a look at the results. The violateddesign rules are listed in the left part of the Error Layer Window (ELW). You can browse the individualviolations by clicking on theleft-/right-arrow buttons on top of the right part of the ELW. The violationwill then also be highlighted in the layout view.

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Figure 5: Design rule check form

Problems:

Finish all connections in the layout. Connect the substrateand the n-well (or possibly, the n-wells) withVSS or with VDD. Examine the layout with the design rule checker to see whether all design rules aresatisfied.

7 Verification

After the layout was drawn and has no design rule errors, it should be verified that it is matched withthe schematic. As previously mentioned, this verification is divided into two steps. In the first step, aprogram, named the extractor, looks into the layout for components and analyzes the connections be-tween the individual components. The result is a netlist. Inthe second step, a further program comparesthis netlist with the netlist of the schematic for agreement. This program is called LVS (Layout VersusSchematic).

The LVS can be started withAssura.Run LVS.... Fill in the form in accordance with Figure 6.Then you can run the LVS by clickingOK in the LVS form. After the comparison is completed, a

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Figure 6: LVS Form

result summary will appear. The wonderful thing isSchematic and Layout Match in this window,which means that there are no discrepancies between layout and schematic. Otherwise, you must locateand correct the errors. Sometimes, this is very time intensive especially for larger circuits. The softwareoffers some support, however, that will not be treated in this exercise. Who is interested in the details, canconsult the documentation in the Cadence. You can evoke it byusing the commandHelp.VirtuosoDocumentation.

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